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/Documentation/devicetree/bindings/interrupt-controller/
Dgoogle,goldfish-pic.txt15 #interrupt-cells = <0x1>;
16 #address-cells = <0>;
23 reg = <0x1f000000 0x1000>;
26 #interrupt-cells = <0x1>;
29 interrupts = <0x2>;
/Documentation/devicetree/bindings/spi/
Dspi-ath79.txt9 - #size-cells: <0>, also as required by generic SPI binding.
17 reg = <0x1f000000 0x10>;
23 #size-cells = <0>;
Dmikrotik,rb4xx-spi.yaml33 #size-cells = <0>;
35 reg = <0x1f000000 0x10>;
Dqca,ar934x-spi.yaml39 reg = <0x1f000000 0x1c>;
42 #size-cells = <0>;
/Documentation/devicetree/bindings/memory-controllers/
Darm,pl172.txt11 first address cell and it may accept values 0..N-1
88 Example for pl172 with nor flash on chip select 0 shown below.
92 reg = <0x40005000 0x1000>;
97 ranges = <0 0 0x1c000000 0x1000000
98 1 0 0x1d000000 0x1000000
99 2 0 0x1e000000 0x1000000
100 3 0 0x1f000000 0x1000000>;
107 mpmc,cs = <0>;
110 mpmc,write-enable-delay = <0>;
111 mpmc,output-enable-delay = <0>;
[all …]
/Documentation/devicetree/bindings/clock/
Dmediatek,mt8192-clock.yaml56 reg = <0x10720000 0x1000>;
63 reg = <0x11007000 0x1000>;
70 reg = <0x11cb1000 0x1000>;
77 reg = <0x11d03000 0x1000>;
84 reg = <0x11d23000 0x1000>;
91 reg = <0x11e01000 0x1000>;
98 reg = <0x11f02000 0x1000>;
105 reg = <0x11f10000 0x1000>;
112 reg = <0x13fbf000 0x1000>;
119 reg = <0x15020000 0x1000>;
[all …]