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/Documentation/devicetree/bindings/usb/
Dux500-usb.txt19 reg = <0xa03e0000 0x10000>;
20 interrupts = <0 23 0x4>;
25 dmas = <&dma 38 0 0x2>, /* Logical - DevToMem */
26 <&dma 38 0 0x0>, /* Logical - MemToDev */
27 <&dma 37 0 0x2>, /* Logical - DevToMem */
28 <&dma 37 0 0x0>, /* Logical - MemToDev */
29 <&dma 36 0 0x2>, /* Logical - DevToMem */
30 <&dma 36 0 0x0>, /* Logical - MemToDev */
31 <&dma 19 0 0x2>, /* Logical - DevToMem */
32 <&dma 19 0 0x0>, /* Logical - MemToDev */
[all …]
Dqcom,pmic-typec.yaml136 #size-cells = <0>;
140 reg = <0x1500>,
141 <0x1700>;
143 interrupts = <0x2 0x15 0x00 IRQ_TYPE_EDGE_RISING>,
144 <0x2 0x15 0x01 IRQ_TYPE_EDGE_BOTH>,
145 <0x2 0x15 0x02 IRQ_TYPE_EDGE_RISING>,
146 <0x2 0x15 0x03 IRQ_TYPE_EDGE_BOTH>,
147 <0x2 0x15 0x04 IRQ_TYPE_EDGE_RISING>,
148 <0x2 0x15 0x05 IRQ_TYPE_EDGE_RISING>,
149 <0x2 0x15 0x06 IRQ_TYPE_EDGE_BOTH>,
[all …]
/Documentation/devicetree/bindings/power/supply/
Dqcom,pmi8998-charger.yaml62 #size-cells = <0>;
67 reg = <0x1000>;
69 interrupts = <0x2 0x12 0x2 IRQ_TYPE_EDGE_BOTH>,
70 <0x2 0x13 0x4 IRQ_TYPE_EDGE_BOTH>,
71 <0x2 0x13 0x6 IRQ_TYPE_EDGE_RISING>,
72 <0x2 0x16 0x1 IRQ_TYPE_EDGE_RISING>;
/Documentation/devicetree/bindings/misc/
Dpvpanic-mmio.txt15 * Bytes 0x0 Write panic event to the reg when guest OS panics.
16 * Bytes 0x1 Reserved.
21 #size-cells = <0x2>;
22 #address-cells = <0x2>;
26 reg = <0x0 0x9060000 0x0 0x2>;
/Documentation/devicetree/bindings/dma/stm32/
Dst,stm32-mdma.yaml17 0x0: Low
18 0x1: Medium
19 0x2: High
20 0x3: Very high
22 -bit 0-1: Source increment mode
23 0x0: Source address pointer is fixed
24 0x2: Source address pointer is incremented after each data transfer
25 0x3: Source address pointer is decremented after each data transfer
27 0x0: Destination address pointer is fixed
28 0x2: Destination address pointer is incremented after each data transfer
[all …]
Dst,stm32-dma3.yaml61 -bit 0-1: The priority level
62 0x0: low priority, low weight
63 0x1: low priority, mid weight
64 0x2: low priority, high weight
65 0x3: high priority
67 0x0: no FIFO requirement/any channel can fit
68 0x2: FIFO of 8 bytes (2^2+1)
69 0x4: FIFO of 32 bytes (2^4+1)
70 0x6: FIFO of 128 bytes (2^6+1)
71 0x7: FIFO of 256 bytes (2^7+1)
[all …]
/Documentation/userspace-api/media/v4l/
Dsubdev-image-processing-full.svg9 xmlns:sodipodi="http://sodipodi.sourceforge.net/DTD/sodipodi-0.dtd"
39 inkscape:pageopacity="0"
45 fit-margin-top="0"
46 fit-margin-left="0"
47 fit-margin-right="0"
48 fit-margin-bottom="0"
67 style="fill:none;fill-opacity:0;stroke:#ff765a;stroke-width:2"
75 style="fill:none;fill-opacity:0;stroke:#000000;stroke-width:2"
91 style="fill:none;fill-opacity:0;stroke:#000000;stroke-width:2"
97 style="fill:none;fill-opacity:0;stroke:#000000;stroke-width:2"
[all …]
Dsubdev-image-processing-scaling-multi-source.svg9 xmlns:sodipodi="http://sodipodi.sourceforge.net/DTD/sodipodi-0.dtd"
39 inkscape:pageopacity="0"
45 fit-margin-top="0"
46 fit-margin-left="0"
47 fit-margin-right="0"
48 fit-margin-bottom="0"
57 style="fill:none;fill-opacity:0;stroke:#000000;stroke-width:2"
74 style="fill:none;fill-opacity:0;stroke:#a52a2a;stroke-width:2"
92 style="fill:none;fill-opacity:0;stroke:#0000ff;stroke-width:2"
152 style="fill:none;fill-opacity:0;stroke:#00ff00;stroke-width:2"
[all …]
Dsubdev-image-processing-crop.svg9 xmlns:sodipodi="http://sodipodi.sourceforge.net/DTD/sodipodi-0.dtd"
39 inkscape:pageopacity="0"
45 fit-margin-top="0"
46 fit-margin-left="0"
47 fit-margin-right="0"
48 fit-margin-bottom="0"
57 style="fill:none;fill-opacity:0;stroke:#000000;stroke-width:2"
74 style="fill:none;fill-opacity:0;stroke:#a52a2a;stroke-width:2"
92 style="fill:none;fill-opacity:0;stroke:#0000ff;stroke-width:2"
166 style="fill:none;fill-opacity:0;stroke:#8b6914;stroke-width:2"
[all …]
/Documentation/input/devices/
Dalps.rst32 E8-E6-E6-E6-E9. An ALPS touchpad should respond with either 00-00-0A or
33 00-00-64 if no buttons are pressed. The bits 0-2 of the first byte will be 1s
45 The new ALPS touchpads have an E7 signature of 73-03-50 or 73-03-0A but
94 byte 0: 0 0 YSGN XSGN 1 M R L
95 byte 1: X7 X6 X5 X4 X3 X2 X1 X0
109 byte 0: 1 0 0 0 1 x9 x8 x7
110 byte 1: 0 x6 x5 x4 x3 x2 x1 x0
111 byte 2: 0 ? ? l r ? fin ges
112 byte 3: 0 ? ? ? ? y9 y8 y7
113 byte 4: 0 y6 y5 y4 y3 y2 y1 y0
[all …]
/Documentation/gpu/
Dafbc.rst31 * Component 0: R
36 fourcc:modifier pair. In general, component '0' is considered to
42 * Component 0: R(8)
49 * Component 0: R(8)
55 * Component 0: Y(8)
65 * Component 0: R(8)
94 * Plane 0:
96 * Component 0: Y(8)
102 * Plane 0:
104 * Component 0: Y(8)
[all …]
/Documentation/devicetree/bindings/powerpc/opal/
Doppanel-opal.txt6 - #lines : Number of lines on the operator panel e.g. <0x2>.
7 - #length : Number of characters per line of the operator panel e.g. <0x10>.
12 #lines = <0x2>;
13 #length = <0x10>;
/Documentation/doc-guide/
Dsvg_image.svg5 width="70px" height="40px" viewBox="0 0 700 400">
6 <line x1="0" y1="200" x2="700" y2="200" stroke="black" stroke-width="20px"/>
8 <line x1="180" y1="370" x2="500" y2="50" stroke="black" stroke-width="15px"/>
9 <polygon points="585 0 525 25 585 50" transform="rotate(135 525 25)"/>
/Documentation/devicetree/bindings/display/ti/
Dti,k2g-dss.yaml85 reg = <0x02540000 0x400>,
86 <0x02550000 0x1000>,
87 <0x02557000 0x1000>,
88 <0x0255a800 0x100>,
89 <0x0255ac00 0x100>;
91 clocks = <&k2g_clks 0x2 0>,
92 <&k2g_clks 0x2 1>;
96 power-domains = <&k2g_pds 0x2>;
/Documentation/devicetree/bindings/nvmem/
Dmediatek,efuse.yaml23 pattern: "^efuse@[0-9a-f]+$"
58 reg = <0x11c10000 0x1000>;
63 reg = <0x184 0x1>;
64 bits = <0 5>;
67 reg = <0x184 0x2>;
71 reg = <0x185 0x1>;
75 reg = <0x186 0x1>;
76 bits = <0 5>;
79 reg = <0x186 0x2>;
83 reg = <0x187 0x1>;
[all …]
/Documentation/devicetree/bindings/regulator/
Drenesas,raa215300.yaml67 x2: x2-clock {
69 #clock-cells = <0>;
75 #size-cells = <0>;
79 reg = <0x12>, <0x6f>;
82 clocks = <&x2>;
/Documentation/hwmon/
Dk10temp.rst10 Socket AM2+: Quad-Core Opteron, Phenom (II) X3/X4, Athlon X2 (but see below)
12 Socket AM3: Quad-Core Opteron, Athlon/Phenom II X2/X3/X4, Sempron II
18 Socket S1G2: Athlon (X2), Sempron (X2), Turion X2 (Ultra)
53 BIOS and Kernel Developer's Guide (BKDG) for AMD Family 14h Models 00h-0Fh Processors:
69 Revision Guide for AMD Family 14h Models 00h-0Fh Processors:
/Documentation/devicetree/bindings/powerpc/fsl/
Dlbc.txt19 reg = <0xf0010100 0x40>;
21 ranges = <0x0 0x0 0xfe000000 0x02000000
22 0x1 0x0 0xf4500000 0x00008000
23 0x2 0x0 0xfd810000 0x00010000>;
25 flash@0,0 {
27 reg = <0x0 0x0 0x2000000>;
32 board-control@1,0 {
33 reg = <0x1 0x0 0x20>;
37 simple-periph@2,0 {
39 reg = <0x2 0x0 0x10000>;
[all …]
/Documentation/devicetree/bindings/net/
Ddavicom,dm9000.yaml54 reg = <0xa8000000 0x2>, <0xa8000002 0x2>;
/Documentation/arch/powerpc/
Dptrace.rst44 #define PPC_DEBUG_FEATURE_INSN_BP_RANGE 0x1
45 #define PPC_DEBUG_FEATURE_INSN_BP_MASK 0x2
46 #define PPC_DEBUG_FEATURE_DATA_BP_RANGE 0x4
47 #define PPC_DEBUG_FEATURE_DATA_BP_MASK 0x8
48 #define PPC_DEBUG_FEATURE_DATA_BP_DAWR 0x10
49 #define PPC_DEBUG_FEATURE_DATA_BP_ARCH_31 0x20
57 #define PPC_BREAKPOINT_TRIGGER_EXECUTE 0x1
58 #define PPC_BREAKPOINT_TRIGGER_READ 0x2
59 #define PPC_BREAKPOINT_TRIGGER_WRITE 0x4
61 #define PPC_BREAKPOINT_MODE_EXACT 0x0
[all …]
/Documentation/devicetree/bindings/pci/
D83xx-512x-pci.txt12 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
14 /* IDSEL 0x0E -mini PCI */
15 0x7000 0x0 0x0 0x1 &ipic 18 0x8
16 0x7000 0x0 0x0 0x2 &ipic 18 0x8
17 0x7000 0x0 0x0 0x3 &ipic 18 0x8
18 0x7000 0x0 0x0 0x4 &ipic 18 0x8
20 /* IDSEL 0x0F - PCI slot */
21 0x7800 0x0 0x0 0x1 &ipic 17 0x8
22 0x7800 0x0 0x0 0x2 &ipic 18 0x8
23 0x7800 0x0 0x0 0x3 &ipic 17 0x8
[all …]
/Documentation/devicetree/bindings/mtd/
Dst,stm32-fmc2-nand.yaml64 - description: Chip select 0 data
65 - description: Chip select 0 command
66 - description: Chip select 0 address space
89 - description: Chip select 0 data
90 - description: Chip select 0 command
91 - description: Chip select 0 address space
105 - description: Chip select 0 data
106 - description: Chip select 0 command
107 - description: Chip select 0 address space
133 reg = <0x58002000 0x1000>,
[all …]
/Documentation/devicetree/bindings/phy/
Dfsl,imx8qm-hsio.yaml57 | pciea-x2-sata | PCIEA| PCIEA| SATA |
59 | pciea-x2-pcieb | PCIEA| PCIEA| PCIEB|
64 enum: [ pciea-x2-sata, pciea-x2-pcieb, pciea-pcieb-sata]
148 reg = <0x5f1a0000 0x10000>,
149 <0x5f120000 0x10000>,
150 <0x5f140000 0x10000>,
151 <0x5f160000 0x10000>;
/Documentation/devicetree/bindings/memory-controllers/
Dst,stm32-fmc2-ebi.yaml51 <bank-number> 0 <address of the bank> <size>
58 "^.*@[0-4],[a-f0-9]+$":
82 reg = <0x58002000 0x1000>;
86 ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */
87 <1 0 0x64000000 0x04000000>, /* EBI CS 2 */
88 <2 0 0x68000000 0x04000000>, /* EBI CS 3 */
89 <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */
90 <4 0 0x80000000 0x10000000>; /* NAND */
92 psram@0,0 {
94 reg = <0 0x00000000 0x100000>;
[all …]
/Documentation/devicetree/bindings/pinctrl/
Dfsl,imxrt1050.yaml72 reg = <0x401f8000 0x4000>;
76 <0x0EC 0x2DC 0x000 0x2 0x0 0xf1>,
77 <0x0F0 0x2E0 0x000 0x2 0x0 0xf1>;

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