Searched +full:0 +full:x200 (Results 1 – 25 of 195) sorted by relevance
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| /Documentation/devicetree/bindings/thermal/ |
| D | rcar-gen3-thermal.yaml | 110 reg = <0xe6198000 0x100>,
111 <0xe61a0000 0x100>,
112 <0xe61a8000 0x100>;
126 thermal-sensors = <&tsc 0>;
144 reg = <0xe6190000 0x200>,
145 <0xe6198000 0x200>,
146 <0xe61a0000 0x200>,
147 <0xe61a8000 0x200>,
148 <0xe61b0000 0x200>;
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| /Documentation/devicetree/bindings/reset/ |
| D | zynq-reset.txt | 9 - reg: SLCR offset and size taken via syscon <0x200 0x48>
19 reg = <0x200 0x48>;
25 0 : soft reset
65 544: a9 reset 0
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| /Documentation/devicetree/bindings/ |
| D | resource-names.txt | 27 ranges = <0 0 0x48000000 0x00001000>, /* MPU path */
28 <1 0 0x49000000 0x00001000>; /* L3 path */
31 reg = <0 0x10 0x10>, <0 0x20 0x10>,
32 <1 0x10 0x10>, <1 0x20 0x10>;
41 reg = <0 0x40 0x10>, <1 0x40 0x10>;
49 reg = <0x4a064000 0x800>, <0x4a064800 0x200>,
50 <0x4a064c00 0x200>;
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| /Documentation/devicetree/bindings/phy/ |
| D | qcom,msm8996-qmp-pcie-phy.yaml | 57 "^phy@[0-9a-f]+$":
92 const: 0
98 const: 0
130 reg = <0x34000 0x488>;
133 ranges = <0x0 0x34000 0x4000>;
149 reg = <0x1000 0x130>,
150 <0x1200 0x200>,
151 <0x1400 0x1dc>;
156 #clock-cells = <0>;
159 #phy-cells = <0>;
[all …]
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| /Documentation/devicetree/bindings/soc/ti/ |
| D | keystone-navigator-dma.txt | 17 |-> DMA instance #0
64 knav_dmas: knav_dmas@0 {
70 ti,navigator-cloud-address = <0x23a80000 0x23a90000
71 0x23aa0000 0x23ab0000>;
73 dma_gbe: dma_gbe@0 {
74 reg = <0x2004000 0x100>,
75 <0x2004400 0x120>,
76 <0x2004800 0x300>,
77 <0x2004c00 0x120>,
78 <0x2005000 0x400>;
[all …]
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| /Documentation/devicetree/bindings/powerpc/fsl/ |
| D | mpic-msgr.txt | 38 Numbers shall start at 0.
49 reg = <0x41400 0x200>;
50 // Message registers 0 and 2 in this block can receive interrupts on
51 // sources 0xb0 and 0xb2, respectively.
52 interrupts = <0xb0 2 0xb2 2>;
53 mpic-msgr-receive-mask = <0x5>;
58 reg = <0x42400 0x200>;
59 // Message registers 0 and 2 in this block can receive interrupts on
60 // sources 0xb4 and 0xb6, respectively.
61 interrupts = <0xb4 2 0xb6 2>;
[all …]
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| /Documentation/devicetree/bindings/display/panel/ |
| D | sharp,lq101r1sx01.yaml | 69 #size-cells = <0>;
70 reg = <0xfd922800 0x200>;
72 panel: panel@0 {
74 reg = <0>;
85 #size-cells = <0>;
86 reg = <0xfd922a00 0x200>;
88 secondary: panel@0 {
90 reg = <0>;
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| /Documentation/devicetree/bindings/mmc/ |
| D | brcm,sdhci-brcmstb.yaml | 90 reg = <0x84b0000 0x260>, <0x84b0300 0x200>;
96 interrupts = <0x0 0x26 0x4>;
105 reg = <0x84b1000 0x260>, <0x84b1300 0x200>;
113 bus-width = <0x8>;
114 interrupts = <0x0 0x27 0x4>;
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| D | npcm,sdhci.yaml | 42 reg = <0xf0840000 0x200>;
43 interrupts = <0 27 4>;
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| /Documentation/sound/cards/ |
| D | joystick.rst | 43 als4000 joystick_port 0 = disable (default), 1 = auto-detect,
44 manual: any address (e.g. 0x200)
46 azf3328 joystick 0 = disable, 1 = enable, -1 = auto (default)
47 ens1370 joystick 0 = disable (default), 1 = enable
48 ens1371 joystick_port 0 = disable (default), 1 = auto-detect,
49 manual: 0x200, 0x208, 0x210, 0x218
50 cmipci joystick_port 0 = disable (default), 1 = auto-detect,
51 manual: any address (e.g. 0x200)
55 es1968 joystick 0 = disable (default), 1 = enable
58 via82xx [#f1]_ joystick 0 = disable (default), 1 = enable
[all …]
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| /Documentation/devicetree/bindings/display/ |
| D | st,stih4xx.txt | 97 - pinctrl-0: pin control handle
124 reg = <0xfe85A800 0x300>;
130 reg = <0xfd348000 0x400>;
136 reg = <0xfe858200 0x300>;
142 reg = <0xfd348400 0x400>;
149 reg = <0xfee82800 0x200>;
156 reg = <0xfee82a00 0x200>;
163 reg = <0xfd349000 0x200>, <0xfd320000 0x10000>;
170 reg = <0xfd349200 0x200>, <0xfd320000 0x10000>;
181 reg = <0xfd340000 0x1000>;
[all …]
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| D | brcm,bcm2711-hdmi.yaml | 117 reg = <0x7ef00700 0x300>,
118 <0x7ef00300 0x200>,
119 <0x7ef00f00 0x80>,
120 <0x7ef00f80 0x80>,
121 <0x7ef01b00 0x200>,
122 <0x7ef01f00 0x400>,
123 <0x7ef00200 0x80>,
124 <0x7ef04300 0x100>,
125 <0x7ef20000 0x100>;
137 resets = <&dvp 0>;
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| /Documentation/gpu/amdgpu/display/ |
| D | trace-groups-table.csv | 2 INFO, 0x1
3 IRQ SVC, 0x2
4 VBIOS, 0x4
5 REGISTER, 0x8
6 PHY DBG, 0x10
7 PSR, 0x20
8 AUX, 0x40
9 SMU, 0x80
10 MALL, 0x100
11 ABM, 0x200
[all …]
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| /Documentation/devicetree/bindings/watchdog/ |
| D | microchip,pic32-wdt.txt | 16 reg = <0x1f800800 0x200>;
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| D | mpc8xxx-wdt.txt | 10 On the 83xx, "Watchdog Timer Registers" area: <0x200 0x100>
11 On the 86xx, "Watchdog Timer Registers" area: <0xe4000 0x100>
12 On the 8xx, "General System Interface Unit" area: <0x0 0x10>
17 On the 83xx, it is located at offset 0x910
18 On the 86xx, it is located at offset 0xe0094
19 On the 8xx, it is located at offset 0x288
22 WDT: watchdog@0 {
24 reg = <0x0 0x10 0x288 0x4>;
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | brcm,bcm2835-armctrl-ic.txt | 21 The 1st cell is the interrupt bank; 0 for interrupts in the "IRQ basic
26 are 0..7 for bank 0, and 0..31 for bank 1.
34 Bank 0:
35 0: ARM_TIMER
45 0: TIMER0
79 0: HOSTPORT
117 reg = <0x7e00b200 0x200>;
125 reg = <0x7e00b200 0x200>;
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| D | jcore,aic.txt | 23 reg = < 0x200 0x30 0x500 0x30 >;
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| /Documentation/devicetree/bindings/display/msm/ |
| D | qcom,sc7280-mdss.yaml | 49 "^display-controller@[0-9a-f]+$":
57 "^displayport-controller@[0-9a-f]+$":
65 "^dsi@[0-9a-f]+$":
75 "^edp@[0-9a-f]+$":
83 "^phy@[0-9a-f]+$":
111 reg = <0xae00000 0x1000>;
130 iommus = <&apps_smmu 0x900 0x402>;
135 reg = <0x0ae01000 0x8f000>,
136 <0x0aeb0000 0x2008>;
154 interrupts = <0>;
[all …]
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| /Documentation/devicetree/bindings/timer/ |
| D | jcore,pit.txt | 22 reg = < 0x200 0x30 0x500 0x30 >;
23 interrupts = < 0x48 >;
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| /Documentation/devicetree/bindings/rtc/ |
| D | mstar,ssd202d-rtc.yaml | 10 - Daniel Palmer <daniel@0x0f.com>
33 reg = <0x6800 0x200>;
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| /Documentation/devicetree/bindings/arm/sunxi/ |
| D | allwinner,sun9i-a80-prcm.yaml | 30 reg = <0x08001400 0x200>;
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| /Documentation/devicetree/bindings/mfd/ |
| D | atmel-matrix.txt | 25 reg = <0xffffec00 0x200>;
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| /Documentation/devicetree/bindings/spi/ |
| D | sqi-pic32.txt | 14 reg = <0x1f8e2000 0x200>;
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| /Documentation/devicetree/bindings/i2c/ |
| D | i2c-img-scb.txt | 13 - #size-cells: Should be <0>
19 reg = <0x18100000 0x200>;
25 #size-cells = <0>;
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| /Documentation/devicetree/bindings/firmware/ |
| D | arm,scpi.yaml | 15 0922B ("ARM Compute Subsystem SCP: Message Interface Protocols")[0] can be
21 [0] http://infocenter.arm.com/help/topic/com.arm.doc.dui0922b/index.html
29 SCPI compliant firmware complying to SCPI v1.0 and above OR
31 prior to SCPI v1.0
33 - const: arm,scpi # SCPI v1.0 and above
34 - const: arm,scpi-pre-1.0 # Unversioned SCPI before v1.0
117 "^clocks-[0-9a-f]+$":
189 scpi_dvfs: clocks-0 {
192 clock-indices = <0>, <1>, <2>;
218 reg = <0x0 0x50000000 0x0 0x10000>;
[all …]
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