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/Documentation/devicetree/bindings/devfreq/event/
Dsamsung,exynos-ppmu.yaml43 '^ppmu-event[0-9]+(-[a-z0-9]+){,2}$':
80 reg = <0x106a0000 0x2000>;
103 reg = <0x112a0000 0x2000>;
118 reg = <0x10480000 0x2000>;
123 reg = <0x10490000 0x2000>;
134 reg = <0x104a0000 0x2000>;
139 reg = <0x104b0000 0x2000>;
144 reg = <0x104c0000 0x2000>;
149 reg = <0x104d0000 0x2000>;
158 reg = <0x106a0000 0x2000>;
/Documentation/devicetree/bindings/net/
Dcortina,gemini-ethernet.yaml38 "^ethernet-port@[0-9]+$":
92 #size-cells = <0>;
106 reg = <0x60000000 0x4000>, /* Global registers, queue */
107 <0x60004000 0x2000>, /* V-bit */
108 <0x60006000 0x2000>; /* A-bit */
113 gmac0: ethernet-port@0 {
115 reg = <0x60008000 0x2000>, /* Port 0 DMA/TOE */
116 <0x6000a000 0x2000>; /* Port 0 GMAC */
128 reg = <0x6000c000 0x2000>, /* Port 1 DMA/TOE */
129 <0x6000e000 0x2000>; /* Port 1 GMAC */
Ddavinci_emac.txt32 reg = <0x220000 0x4000>;
33 ti,davinci-ctrl-reg-offset = <0x3000>;
34 ti,davinci-ctrl-mod-reg-offset = <0x2000>;
35 ti,davinci-ctrl-ram-offset = <0>;
36 ti,davinci-ctrl-ram-size = <0x2000>;
Dingenic,mac.yaml22 - ingenic,x2000-mac
66 reg = <0x134b0000 0x2000>;
/Documentation/devicetree/bindings/remoteproc/
Dti,pru-rproc.yaml19 The K3 SoCs containing ICSSG v1.0 (eg: AM65x SR1.0) also have two Auxiliary
21 containing the revised ICSSG v1.1 (eg: J721E, AM65x SR2.0) have an extra two
46 - ti,am654-tx-pru # for Tx_PRUs in K3 AM65x SR2.0 SoCs
90 pattern: "^rtu@[0-9a-f]+$"
102 pattern: "^txpru@[0-9a-f]+"
106 pattern: "^pru@[0-9a-f]+$"
119 pruss_tm: target-module@300000 { /* 0x4a300000, ap 9 04.0 */
123 ranges = <0x0 0x300000 0x80000>;
125 pruss: pruss@0 {
127 reg = <0x0 0x80000>;
[all …]
/Documentation/devicetree/bindings/soc/ti/
Dti,pruss.yaml36 0x0, but also has access to a secondary Data RAM (primary to the other PRU
37 core) at its address 0x2000. A shared Data RAM, if present, can be accessed
60 pattern: "^(pruss|icssg)@[0-9a-f]+$"
65 - ti,am4376-pruss0 # for AM437x SoC family and PRUSS unit 0
161 const: 0
175 const: 0
209 const: 0
317 "^(pru|rtu|txpru)@[0-9a-f]+$":
370 pruss: pruss@0 {
372 reg = <0x0 0x80000>;
[all …]
/Documentation/devicetree/bindings/arm/hisilicon/controller/
Dcpuctrl.yaml33 "^clock@[0-9a-f]+$":
65 reg = <0x00a22000 0x2000>;
66 ranges = <0 0x00a22000 0x2000>;
68 clock: clock@0 {
70 reg = <0 0x2000>;
/Documentation/devicetree/bindings/arm/omap/
Dctrl.txt41 reg = <0x2000 0x2000>;
44 ranges = <0 0x2000 0x2000>;
49 reg = <0x30 0x230>;
51 #size-cells = <0>;
55 pinctrl-single,function-mask = <0xff1f>;
60 reg = <0x270 0x330>;
66 #size-cells = <0>;
76 #clock-cells = <0>;
80 reg = <0x02d8>;
/Documentation/devicetree/bindings/pci/
Dmvebu-pci.txt23 0x82000000 0 r MBUS_ID(0xf0, 0x01) r 0 s
32 registers area. This range entry translates the '0x82000000 0 r' PCI
33 address into the 'MBUS_ID(0xf0, 0x01) r' CPU address, which is part
34 of the internal register window (as identified by MBUS_ID(0xf0,
35 0x01)).
39 0x8t000000 s 0 MBUS_ID(w, a) 0 1 0
79 value is 0.
99 bus-range = <0x00 0xff>;
103 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
104 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
[all …]
Daxis,artpec6-pcie.txt28 reg = <0xf8050000 0x2000
29 0xf8040000 0x1000
30 0xc0000000 0x2000>;
36 ranges = <0x81000000 0 0 0xc0002000 0 0x00010000
38 0x82000000 0 0xc0012000 0xc0012000 0 0x1ffee000>;
40 bus-range = <0x00 0xff>;
44 interrupt-map-mask = <0 0 0 0x7>;
45 interrupt-map = <0 0 0 1 &intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
46 <0 0 0 2 &intc GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
47 <0 0 0 3 &intc GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
[all …]
/Documentation/devicetree/bindings/cache/
Dsocionext,uniphier-system-cache.yaml69 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>;
70 interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>;
72 cache-size = <0x140000>;
82 reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, <0x506c0000 0x400>;
83 interrupts = <0 190 4>, <0 191 4>;
85 cache-size = <0x200000>;
94 reg = <0x500c8000 0x2000>, <0x503c8100 0x8>, <0x506c8000 0x400>;
95 interrupts = <0 174 4>, <0 175 4>;
97 cache-size = <0x200000>;
/Documentation/devicetree/bindings/pinctrl/
Dingenic,pinctrl.yaml18 which the pin is associated and N is an integer from 0 to 31 identifying the
22 pins. The X2000 and the X2100 contains 5 GPIO ports, PA to PE, for a total of
46 - ingenic,x2000-pinctrl
56 - const: ingenic,x2000-pinctrl
65 const: 0
68 "^gpio@[0-9]$":
85 - ingenic,x2000-gpio
170 reg = <0x10010000 0x600>;
173 #size-cells = <0>;
175 gpio@0 {
[all …]
/Documentation/devicetree/bindings/interrupt-controller/
Darm,gic-v3.yaml33 enum: [ 0, 1, 2 ]
46 The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI
51 SPI interrupts are in the range [0-987]. PPI interrupts are in the
52 range [0-15]. Extended SPI interrupts are in the range [0-1023].
53 Extended PPI interrupts are in the range [0-127].
56 bits[3:0] trigger type and level flags.
68 of 0 if present.
83 ARMv8.0 architecture such as Cortex-A32, A34, A35, A53, A57, A72 and
99 multipleOf: 0x10000
100 exclusiveMinimum: 0
[all …]
/Documentation/devicetree/bindings/sound/
Dqcom,wcd939x-sdw.yaml49 #size-cells = <0>;
50 reg = <0x03210000 0x2000>;
51 wcd938x_rx: codec@0,4 {
53 reg = <0 4>;
60 #size-cells = <0>;
61 reg = <0x03230000 0x2000>;
62 wcd938x_tx: codec@0,3 {
64 reg = <0 3>;
Dqcom,wcd938x-sdw.yaml50 #size-cells = <0>;
51 reg = <0x03210000 0x2000>;
52 wcd938x_rx: codec@0,4 {
54 reg = <0 4>;
61 #size-cells = <0>;
62 reg = <0x03230000 0x2000>;
63 wcd938x_tx: codec@0,3 {
65 reg = <0 3>;
Dqcom,wcd938x.yaml58 #size-cells = <0>;
59 reg = <0x03210000 0x2000>;
60 wcd938x_rx: codec@0,4 {
62 reg = <0 4>;
69 #size-cells = <0>;
70 reg = <0x03230000 0x2000>;
71 wcd938x_tx: codec@0,3 {
73 reg = <0 3>;
Dqcom,wcd937x.yaml43 pinctrl-0 = <&wcd_reset_n>;
62 reg = <0x03210000 0x2000>;
64 #size-cells = <0>;
65 wcd937x_rx: codec@0,4 {
67 reg = <0 4>;
73 reg = <0x03230000 0x2000>;
75 #size-cells = <0>;
76 wcd937x_tx: codec@0,3 {
78 reg = <0 3>;
/Documentation/devicetree/bindings/mfd/
Dmxs-lradc.txt27 reg = <0x80050000 0x2000>;
39 reg = <0x80050000 0x2000>;
/Documentation/devicetree/bindings/soc/socionext/
Dsocionext,uniphier-soc-glue-debug.yaml45 "^efuse@[0-9a-f]+$":
59 reg = <0x5f900000 0x2000>;
62 ranges = <0 0x5f900000 0x2000>;
66 reg = <0x100 0x28>;
/Documentation/devicetree/bindings/dma/
Dfsl,mxs-dma.yaml75 reg = <0x80004000 0x2000>;
79 87 86 0 0>;
86 reg = <0x80024000 0x2000>;
87 interrupts = <78 79 66 0
/Documentation/devicetree/bindings/phy/
Dmediatek,mt8365-csi-rx.yaml32 enum: [0, 1]
34 If the PHY doesn't support mode selection then #phy-cells must be 0 and
66 reg = <0 0x11c10000 0 0x2000>;
73 reg = <0 0x11c12000 0 0x2000>;
76 #phy-cells = <0>;
/Documentation/devicetree/bindings/goldfish/
Dpipe.txt15 reg = <ff018000 0x2000>;
16 interrupts = <0x12>;
/Documentation/devicetree/bindings/power/reset/
Daxxia-reset.txt14 reg = <0x20 0x10030000 0 0x2000>;
/Documentation/gpu/amdgpu/display/
Dtrace-groups-table.csv2 INFO, 0x1
3 IRQ SVC, 0x2
4 VBIOS, 0x4
5 REGISTER, 0x8
6 PHY DBG, 0x10
7 PSR, 0x20
8 AUX, 0x40
9 SMU, 0x80
10 MALL, 0x100
11 ABM, 0x200
[all …]
/Documentation/devicetree/bindings/mtd/
Ddiskonchip.txt12 docg3: flash@0 {
14 reg = <0x0 0x2000>;

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