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/Documentation/devicetree/bindings/soc/qcom/
Dqcom,smem.yaml60 reg = <0xfa00000 0x200000>;
73 reg = <0xfa00000 0x200000>;
94 reg = <0xfc428000 0x4000>;
/Documentation/devicetree/bindings/pinctrl/
Dqcom,qcs404-pinctrl.yaml64 - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-1][0-9])$"
134 reg = <0x01000000 0x200000>,
135 <0x01300000 0x200000>,
136 <0x07b00000 0x200000>;
139 gpio-ranges = <&tlmm 0 0 120>;
/Documentation/gpu/amdgpu/display/
Dtrace-groups-table.csv2 INFO, 0x1
3 IRQ SVC, 0x2
4 VBIOS, 0x4
5 REGISTER, 0x8
6 PHY DBG, 0x10
7 PSR, 0x20
8 AUX, 0x40
9 SMU, 0x80
10 MALL, 0x100
11 ABM, 0x200
[all …]
/Documentation/devicetree/bindings/cache/
Dsocionext,uniphier-system-cache.yaml69 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>;
70 interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>;
72 cache-size = <0x140000>;
82 reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, <0x506c0000 0x400>;
83 interrupts = <0 190 4>, <0 191 4>;
85 cache-size = <0x200000>;
94 reg = <0x500c8000 0x2000>, <0x503c8100 0x8>, <0x506c8000 0x400>;
95 interrupts = <0 174 4>, <0 175 4>;
97 cache-size = <0x200000>;
/Documentation/devicetree/bindings/mtd/
Dingenic,nand.yaml66 reg = <0x13410000 0x10000>;
69 ranges = <1 0 0x1b000000 0x1000000>,
70 <2 0 0x1a000000 0x1000000>,
71 <3 0 0x19000000 0x1000000>,
72 <4 0 0x18000000 0x1000000>,
73 <5 0 0x17000000 0x1000000>,
74 <6 0 0x16000000 0x1000000>;
80 reg = <1 0 0x1000000>;
83 #size-cells = <0>;
94 pinctrl-0 = <&pins_nemc>;
[all …]
Dorion-nand.txt9 - cle : Address line number connected to CLE. Default is 0
23 cle = <0>;
28 reg = <0xf4000000 0x400>;
30 partition@0 {
32 reg = <0x0000000 0x100000>;
38 reg = <0x0100000 0x200000>;
43 reg = <0x0300000 0x100000>;
48 reg = <0x0400000 0x7d00000>;
Dnxp-spifi.txt5 mode 0 or 3. The controller operates in either command or memory
25 - spi-cpol : Controller only supports mode 0 and 3 so either
37 reg = <0x40003000 0x1000>, <0x14000000 0x4000000>;
44 flash@0 {
52 partition@0 {
54 reg = <0 0x200000>;
/Documentation/devicetree/bindings/net/
Dipq806x-dwmac.txt23 reg = <0x37000000 0x200000>;
Dqcom,ipq8064-mdio.yaml44 #size-cells = <0>;
47 reg = <0x37000000 0x200000>;
53 reg = <0x10>;
57 #size-cells = <0>;
/Documentation/devicetree/bindings/mtd/partitions/
Dfixed-partitions.yaml51 "@[0-9a-f]+$":
77 partition@0 {
79 reg = <0x0000000 0x100000>;
84 reg = <0x0100000 0x200000>;
96 partition@0 {
98 reg = <0x00000000 0x1 0x00000000>;
110 partition@0 {
112 reg = <0x0 0x00000000 0x2 0x00000000>;
118 reg = <0x2 0x00000000 0x1 0x00000000>;
128 partition@0 {
[all …]
Dbinman.yaml43 reg = <0x100000 0xf00000>;
44 align-size = <0x1000>;
45 align-end = <0x10000>;
50 reg = <0x200000 0x100000>;
51 align = <0x4000>;
Dlinksys,ns-partitions.yaml34 "^partition@[0-9a-f]+$":
56 partition@0 {
58 reg = <0x0 0x100000>;
64 reg = <0x100000 0x100000>;
69 reg = <0x200000 0xf00000>;
74 reg = <0x1100000 0xf00000>;
/Documentation/devicetree/bindings/phy/
Dphy-da8xx-usb.txt8 controllers on DA8xx SoCs. Consumers of this device should use index 0 for
18 reg = <0x1417c 0x14>;
28 reg = <0x200000 0x1000>;
30 phys = <&usb_phy 0>;
36 reg = <0x225000 0x1000>;
/Documentation/devicetree/bindings/edac/
Ddmc-520.yaml58 reg = <0x200000 0x80000>;
59 interrupts = <0x0 0x349 0x4>, <0x0 0x34B 0x4>;
/Documentation/devicetree/bindings/clock/
Dqcom,sc7180-dispcc.yaml57 reg = <0x0af00000 0x200000>;
60 <&dsi_phy 0>,
62 <&dp_phy 0>,
Dqcom,sc7280-dispcc.yaml61 reg = <0x0af00000 0x200000>;
64 <&dsi_phy 0>,
66 <&dp_phy 0>,
68 <&edp_phy 0>,
Dqcom,x1e80100-gcc.yaml31 - description: USB QMP Phy 0 clock source
56 reg = <0x00100000 0x200000>;
64 <&usb_1_ss0_qmpphy 0>,
Dqcom,sm7150-dispcc.yaml59 reg = <0x0af00000 0x200000>;
64 <&mdss_dsi0_phy 0>,
66 <&mdss_dsi1_phy 0>,
68 <&dp_phy 0>,
/Documentation/driver-api/media/drivers/
Dsaa7134-devel.rst14 - 32.11 MHz -> .audio_clock=0x187de7
15 - 24.576MHz -> .audio_clock=0x200000 (xtal * .audio_clock = 51539600)
49 - 0=Radio 1=TV
/Documentation/devicetree/bindings/crypto/
Dinside-secure,safexcel.yaml76 reg = <0x800000 0x200000>;
/Documentation/devicetree/bindings/usb/
Dbrcm,usb-pinmap.yaml63 reg = <0x22000d0 0x4>;
64 in-gpios = <&gpio 18 0>, <&gpio 19 0>;
66 brcm,in-masks = <0x8000 0x40000 0x10000 0x80000>;
67 out-gpios = <&gpio 20 0>;
69 brcm,out-masks = <0x20000 0x800000 0x400000 0x200000>;
70 interrupts = <0x0 0xb2 0x4>;
/Documentation/devicetree/bindings/ata/
Drenesas,rcar-sata.yaml79 reg = <0xee300000 0x200000>;
/Documentation/devicetree/bindings/mailbox/
Dbrcm,iproc-flexrm-mbox.txt45 reg = <0x67000000 0x200000>;
46 msi-parent = <&gic_its 0x7f00>;
52 reg = <0x672c0000 0x1000>;
53 mboxes = <&crypto_mbox 0 0x1 0xffff>,
54 <&crypto_mbox 1 0x1 0xffff>,
55 <&crypto_mbox 16 0x1 0xffff>,
56 <&crypto_mbox 17 0x1 0xffff>,
57 <&crypto_mbox 30 0x1 0xffff>,
58 <&crypto_mbox 31 0x1 0xffff>;
/Documentation/devicetree/bindings/pci/
Drcar-pci-ep.yaml79 reg = <0xfe000000 0x80000>,
80 <0xfe100000 0x100000>,
81 <0xfe200000 0x200000>,
82 <0x30000000 0x8000000>,
83 <0x38000000 0x8000000>;
/Documentation/devicetree/bindings/leds/
Dregister-bit-led.yaml26 pattern: '^led@[0-9a-f]+,[0-9a-f]{1,2}$'
41 [ 0x1, 0x2, 0x4, 0x8, 0x10, 0x20, 0x40, 0x80, 0x100, 0x200, 0x400, 0x800,
42 0x1000, 0x2000, 0x4000, 0x8000, 0x10000, 0x20000, 0x40000, 0x80000,
43 0x100000, 0x200000, 0x400000, 0x800000, 0x1000000, 0x2000000, 0x4000000,
44 0x8000000, 0x10000000, 0x20000000, 0x40000000, 0x80000000 ]
64 reg = <0x10000000 0x1000>;
67 ranges = <0x0 0x10000000 0x1000>;
69 led@8,0 {
71 reg = <0x08 0x04>;
72 offset = <0x08>;
[all …]

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