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/Documentation/dev-tools/
Dkfence.rst29 CONFIG_KFENCE_SAMPLE_INTERVAL=0
41 ``CONFIG_KFENCE_SAMPLE_INTERVAL``. Setting ``kfence.sample_interval=0``
87 BUG: KFENCE: out-of-bounds read in test_out_of_bounds_read+0xa6/0x234
89 Out-of-bounds read at 0xffff8c3f2e291fff (1B left of kfence-#72):
90 test_out_of_bounds_read+0xa6/0x234
91 kunit_try_run_case+0x61/0xa0
92 kunit_generic_run_threadfn_adapter+0x16/0x30
93 kthread+0x176/0x1b0
94 ret_from_fork+0x22/0x30
96 kfence-#72: 0xffff8c3f2e292000-0xffff8c3f2e29201f, size=32, cache=kmalloc-32
[all …]
Dkcsan.rst32 write to 0xffffffffc009a628 of 8 bytes by task 487 on cpu 0:
33 test_kernel_write+0x1d/0x30
34 access_thread+0x89/0xd0
35 kthread+0x23e/0x260
36 ret_from_fork+0x22/0x30
38 read to 0xffffffffc009a628 of 8 bytes by task 488 on cpu 6:
39 test_kernel_read+0x10/0x20
40 access_thread+0x89/0xd0
41 kthread+0x23e/0x260
42 ret_from_fork+0x22/0x30
[all …]
/Documentation/devicetree/bindings/serial/
Drenesas,scifa.yaml104 reg = <0xe6c40000 64>;
110 dmas = <&dmac0 0x21>, <&dmac0 0x22>, <&dmac1 0x21>, <&dmac1 0x22>;
/Documentation/leds/
Dleds-mlxcpld.rst28 - CPLD reg offset: 0x20
29 - Bits [3:0]
32 - CPLD reg offset: 0x20
36 - CPLD reg offset: 0x21
37 - Bits [3:0]
40 - CPLD reg offset: 0x21
44 - CPLD reg offset: 0x22
45 - Bits [3:0]
48 - CPLD reg offset: 0x22
56 - [0,0,0,0] = LED OFF
[all …]
/Documentation/networking/
Dmac80211-injection.rst75 0x00, 0x00, // <-- radiotap version
76 0x0b, 0x00, // <- radiotap header length
77 0x04, 0x0c, 0x00, 0x00, // <-- bitmap
78 0x6c, // <-- rate
79 0x0c, //<-- tx power
80 0x01 //<-- antenna
85 0x08, 0x01, 0x00, 0x00,
86 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
87 0x13, 0x22, 0x33, 0x44, 0x55, 0x66,
88 0x13, 0x22, 0x33, 0x44, 0x55, 0x66,
[all …]
/Documentation/devicetree/bindings/spi/
Dspi-sunplus-sp7021.yaml55 - pinctrl-0
64 reg = <0x9c002d80 0x80>, <0x9c002e00 0x80>;
73 clocks = <&clkc 0x32>;
74 resets = <&rstc 0x22>;
76 pinctrl-0 = <&pins_spi0>;
/Documentation/translations/zh_CN/dev-tools/
Dkcsan.rst35 write to 0xffffffffc009a628 of 8 bytes by task 487 on cpu 0:
36 test_kernel_write+0x1d/0x30
37 access_thread+0x89/0xd0
38 kthread+0x23e/0x260
39 ret_from_fork+0x22/0x30
41 read to 0xffffffffc009a628 of 8 bytes by task 488 on cpu 6:
42 test_kernel_read+0x10/0x20
43 access_thread+0x89/0xd0
44 kthread+0x23e/0x260
45 ret_from_fork+0x22/0x30
[all …]
/Documentation/devicetree/bindings/power/supply/
Drichtek,rt9455.yaml73 #size-cells = <0>;
77 reg = <0x22>;
80 interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
Dbattery.yaml126 '^ocv-capacity-table-[0-9]+$':
146 #size-cells = <0>;
162 ocv-capacity-celsius = <(-10) 0 10>;
164 ocv-capacity-table-0 = <4185000 100>, <4113000 95>, <4066000 90>;
165 /* table for 0 degree Celsius */
169 resistance-temp-table = <20 100>, <10 90>, <0 80>, <(-10) 60>;
172 alert-celsius = <0 40>;
176 reg = <0x11>;
181 reg = <0x22>;
/Documentation/devicetree/bindings/input/touchscreen/
Dti,am3359-tsc.yaml41 input lines and terminals respectively are as follows, AIN0 = 0, AIN1 = 1
42 and so on until AIN7 = 7. XP = 0, XN = 1, YP = 2, YN = 3.
52 lower value, say 0x400, and increase value until false pen-up events are
74 ti,wire-config = <0x00 0x11 0x22 0x33>;
75 ti,charge-delay = <0x400>;
/Documentation/devicetree/bindings/mfd/
Dcirrus,lochnagar.yaml57 const: 0x22
273 #size-cells = <0>;
274 reg = <0xe0004000 0x1000>;
278 reg = <0x22>;
280 reset-gpios = <&gpio0 55 0>;
281 present-gpios = <&gpio0 60 0>;
297 #clock-cells = <0>;
306 gpio-ranges = <&lochnagar 0 0 LOCHNAGAR2_PIN_NUM_GPIOS>;
309 pinctrl-0 = <&pinsettings>;
/Documentation/devicetree/bindings/sound/
Deverest,es8326.yaml28 const: 0
35 Bit(1)/(0) decides the mic property to be OMTP/CTIA or auto.
36 minimum: 0x00
37 maximum: 0x0f
38 default: 0x0f
45 minimum: 0x00
46 maximum: 0x77
47 default: 0x22
54 minimum: 0x00
55 maximum: 0x77
[all …]
/Documentation/devicetree/bindings/usb/
Dti,tps6598x.yaml33 The patch address can be any value except 0x00, 0x20,
34 0x21, 0x22, and 0x23
101 #size-cells = <0>;
105 reg = <0x38>;
113 pinctrl-0 = <&typec_pins>;
132 #size-cells = <0>;
136 reg = <0x21>, <0x0f>;
145 pinctrl-0 = <&typec_pins>;
/Documentation/devicetree/bindings/perf/
Dapm-xgene-pmu.txt43 reg = <0x0 0x7e200000 0x0 0x1000>;
48 reg = <0x0 0x7e700000 0x0 0x1000>;
53 reg = <0x0 0x7e720000 0x0 0x1000>;
64 reg = <0x0 0x78810000 0x0 0x1000>;
65 interrupts = <0x0 0x22 0x4>;
69 reg = <0x0 0x7e610000 0x0 0x1000>;
74 reg = <0x0 0x7e940000 0x0 0x1000>;
79 reg = <0x0 0x7e710000 0x0 0x1000>;
80 enable-bit-index = <0>;
85 reg = <0x0 0x7e730000 0x0 0x1000>;
[all …]
/Documentation/devicetree/bindings/media/
Drenesas,drif.yaml113 enum: [0, 1]
115 Indicates sync signal polarity, 0/1 for low/high respectively.
137 - pinctrl-0
146 - pinctrl-0
150 pinctrl-0: false
179 reg = <0 0xe6f40000 0 0x64>;
183 dmas = <&dmac1 0x20>, <&dmac2 0x20>;
189 pinctrl-0 = <&drif0_pins>;
201 reg = <0 0xe6f50000 0 0x64>;
205 dmas = <&dmac1 0x22>, <&dmac2 0x22>;
[all …]
/Documentation/hwmon/
Dw83781d.rst10 Addresses scanned: I2C 0x28 - 0x2f, ISA 0x290 (8 I/O ports)
18 Addresses scanned: I2C 0x28 - 0x2f, ISA 0x290 (8 I/O ports)
26 Addresses scanned: I2C 0x2d
34 Addresses scanned: I2C 0x28 - 0x2f
52 Use 'init=0' to bypass initializing the chip.
56 (default 0)
62 a certain chip. Typical usage is `force_subclients=0,0x2d,0x4a,0x4b`
63 to force the subclients of chip 0x2d on bus 0 to i2c addresses
64 0x4a and 0x4b. This parameter is useful for certain Tyan boards.
80 | as99127f | 7 | 3 | 0 | 3 | 0x31 | 0x12c3 | yes | no |
[all …]
/Documentation/admin-guide/perf/
Ddwc_pcie_pmu.rst31 - Group#0: Percentage of time the controller stays in LTSSM states.
63 "Rx_PCIe_TLP_Data_Payload" is an equivalent of "eventid=0x22,type=0x1".
/Documentation/devicetree/bindings/media/xilinx/
Dxlnx,csi2rxss.yaml53 0x1e - YUV4228B
54 0x1f - YUV42210B
55 0x20 - RGB444
56 0x21 - RGB555
57 0x22 - RGB565
58 0x23 - RGB666
59 0x24 - RGB888
60 0x28 - RAW6
61 0x29 - RAW7
62 0x2a - RAW8
[all …]
/Documentation/devicetree/bindings/gpio/
Dgpio-pca95xx.yaml108 "^(hog-[0-9]+|.+-hog(-[0-9]+)?)$":
147 #size-cells = <0>;
151 reg = <0x20>;
153 pinctrl-0 = <&pinctrl_pca9505>;
173 #size-cells = <0>;
177 reg = <0x22>;
199 #size-cells = <0>;
204 reg = <0x6d>;
217 #size-cells = <0>;
222 reg = <0x6e>;
/Documentation/driver-api/surface_aggregator/clients/
Ddtx.rst171 - ``0x0000``
175 - ``0x1000``
179 - ``0x2000``
183 - ``0xF000``
208 - ``0x1001``
213 - ``0x1002``
218 - ``0x2001``
223 - ``0x2002``
228 - ``0x2003``
245 - ``0x0000``
[all …]
/Documentation/RCU/
Dlockdep-splat.rst30 rcu_scheduler_active = 1, debug_locks = 0
32 #0: (&shost->scan_mutex){+.+.}, at: [<ffffffff8145efca>]
33 scsi_scan_host_selected+0x5a/0x150
35 elevator_exit+0x22/0x60
37 cfq_exit_queue+0x43/0x190
40 Pid: 1552, comm: scsi_scan_6 Not tainted 3.0.0-rc5 #17
42 [<ffffffff810abb9b>] lockdep_rcu_dereference+0xbb/0xc0
43 [<ffffffff812b6139>] __cfq_exit_single_io_context+0xe9/0x120
44 [<ffffffff812b626c>] cfq_exit_queue+0x7c/0x190
45 [<ffffffff812a5046>] elevator_exit+0x36/0x60
[all …]
/Documentation/devicetree/bindings/iio/adc/
Dmicrochip,mcp3564.yaml81 minimum: 0
85 configured on request. If not requested, the fuses are set for 0x1.
101 const: 0
104 "^channel@([0-9]|([1-7][0-9]))$":
113 minimum: 0
153 #size-cells = <0>;
155 adc@0 {
157 reg = <0>;
165 #size-cells = <0>;
167 channel@0 {
[all …]
/Documentation/fb/
Dmatroxfb.rst31 pass to the kernel this command line: "video=matroxfb:vesa:0x1BB".
35 unless you have primary display on non-Matrox VBE2.0 device (see
48 4 0x12 0x102
49 8 0x100 0x101 0x180 0x103 0x188
50 15 0x110 0x181 0x113 0x189
51 16 0x111 0x182 0x114 0x18A
52 24 0x1B2 0x184 0x1B5 0x18C
53 32 0x112 0x183 0x115 0x18B
63 4 0x104 0x106
64 8 0x105 0x190 0x107 0x198 0x11C
[all …]
/Documentation/w1/slaves/
Dw1_therm.rst24 W1_THERM_DS18S20 0x10
25 W1_THERM_DS1822 0x22
26 W1_THERM_DS18B20 0x28
27 W1_THERM_DS1825 0x3B
28 W1_THERM_DS28EA00 0x42
48 ``therm_bulk_read`` will return 0 if no bulk conversion pending,
68 the default conversion time write ``0`` to ``conv_time``.
74 To store the current resolution in EEPROM, write ``0`` to ``w1_slave``.
91 ``0`` if the device is parasite powered, ``1`` if the device is externally powered.
99 The module parameter strong_pullup can be set to 0 to disable the
[all …]
/Documentation/devicetree/bindings/dma/ti/
Dk3-bcdma.yaml50 0 - split channel
56 if cell 1 is 0 (split channel):
59 for source thread IDs (rx): 0 - 0x7fff
60 for destination thread IDs (tx): 0x8000 - 0xffff
95 maximum: 0x3f
106 maximum: 0x3f
117 maximum: 0x3f
241 reg = <0x0 0x485c0100 0x0 0x100>,
242 <0x0 0x4c000000 0x0 0x20000>,
243 <0x0 0x4a820000 0x0 0x20000>,
[all …]

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