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/Documentation/devicetree/bindings/pinctrl/
Dfsl,imx8m-pinctrl.yaml81 reg = <0x30330000 0x10000>;
85 <0x23C 0x4A4 0x4FC 0x0 0x0 0x140>,
86 <0x240 0x4A8 0x000 0x0 0x0 0x140>;
/Documentation/devicetree/bindings/soc/imx/
Dfsl,imx8mp-hdmi-blk-ctrl.yaml84 reg = <0x32fc0000 0x23c>;
/Documentation/trace/coresight/
Dcoresight-cpu-debug.rst52 If PCSROffset=0b0000, on ARMv8-a the feature of EDPCSR is not implemented;
59 If PCSROffset=0b0010, ARMv8-a defines "EDPCSR implemented, and samples have
61 state". So on ARMv8 if EDDEVID1.PCSROffset is 0b0010 and the CPU operates
143 To disable it, write a '0' into /sys/kernel/debug/coresight_cpu_debug/enable::
145 # echo 0 > /sys/kernel/debug/coresight_cpu_debug/enable
165 # exec 3<> /dev/cpu_dma_latency; echo 0 >&3
184 coresight-cpu-debug 850000.debug: CPU[0]:
186 coresight-cpu-debug 850000.debug: EDPCSR: handle_IPI+0x174/0x1d8
188 …esight-cpu-debug 850000.debug: EDVIDSR: 90000000 (State:Non-secure Mode:EL1/0 Width:64bits VMID:0)
191 coresight-cpu-debug 852000.debug: EDPCSR: debug_notifier_call+0x23c/0x358
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/Documentation/arch/x86/
Dboot.rst28 Protocol 2.02 (Kernel 2.4.0-test3-pre3) New command line protocol.
99 0A0000 +------------------------+
121 0x100000 ("high memory"), and the kernel real-mode block (boot sector,
123 0x10000 and end of low memory. Unfortunately, in protocols 2.00 and
124 2.01 the 0x90000+ memory range is still used internally by the kernel;
139 0x90000 segment, the boot loader should make sure not to use memory
140 above the 0x9A000 point; too many BIOSes will break above that point.
149 0A0000 +------------------------+
180 following header at offset 0x01f1. The real-mode code can total up to
195 01FE/2 ALL boot_flag 0xAA55 magic number
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