Searched +full:0 +full:x28 (Results 1 – 25 of 94) sorted by relevance
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| /Documentation/devicetree/bindings/mfd/ |
| D | brcm,twd.yaml | 54 reg = <0xff800400 0x4c>;
55 ranges = <0x00000000 0xff800400 0x4c>;
60 timer@0 {
62 reg = <0x0 0x28>;
67 reg = <0x28 0x8>;
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| /Documentation/devicetree/bindings/arm/freescale/ |
| D | tigerp.txt | 11 reg = <0x83fa0000 0x28>;
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| /Documentation/hwmon/ |
| D | lm80.rst | 10 Addresses scanned: I2C 0x28 - 0x2f
20 Addresses scanned: I2C 0x28 - 0x2f
63 inputs can measure voltages between 0 and 2.55 volts, with a resolution
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| D | lm78.rst | 10 Addresses scanned: I2C 0x28 - 0x2f, ISA 0x290 (8 I/O ports)
20 Addresses scanned: I2C 0x28 - 0x2f, ISA 0x290 (8 I/O ports)
64 inputs can measure voltages between 0 and 4.08 volts, with a resolution
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| /Documentation/devicetree/bindings/timer/ |
| D | via,vt8500-timer.txt | 13 reg = <0xd8130100 0x28>;
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| /Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/ |
| D | ucc.txt | 15 - port-number : for UART drivers, the port number to use, between 0 and 3.
16 This usually corresponds to the /dev/ttyQE device, e.g. <0> = /dev/ttyQE0.
36 0x00 : clock source is disabled;
37 0x1~0x10 : clock source is BRG1~BRG16 respectively;
38 0x11~0x28: clock source is QE_CLK1~QE_CLK24 respectively.
40 0x00 : clock source is disabled;
41 0x1~0x10 : clock source is BRG1~BRG16 respectively;
42 0x11~0x28: clock source is QE_CLK1~QE_CLK24 respectively.
60 interrupts = <a0 0>;
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| /Documentation/devicetree/bindings/rng/ |
| D | brcm,iproc-rng200.yaml | 29 reg = <0x18032000 0x28>;
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| /Documentation/devicetree/bindings/sound/ |
| D | realtek,rt1019.yaml | 30 #size-cells = <0>;
33 reg = <0x28>;
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| D | realtek,rt1015.yaml | 35 #size-cells = <0>;
38 reg = <0x28>;
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| /Documentation/devicetree/bindings/hwmon/ |
| D | adi,ad741x.yaml | 33 #size-cells = <0>;
37 reg = <0x28>;
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| D | winbond,w83781d.yaml | 35 #size-cells = <0>;
39 reg = <0x28>;
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| /Documentation/devicetree/bindings/phy/ |
| D | brcm,kona-usb2-phy.yaml | 20 const: 0
33 reg = <0x3f130000 0x28>;
34 #phy-cells = <0>;
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| D | intel,lgm-usb-phy.yaml | 35 const: 0
51 reg = <0xe7e00000 0x10000>;
53 resets = <&rcu 0x70 0x24>,
54 <&rcu 0x70 0x26>,
55 <&rcu 0x70 0x28>;
57 #phy-cells = <0>;
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| /Documentation/devicetree/bindings/reset/ |
| D | sunplus,reset.yaml | 34 reg = <0x9c000054 0x28>;
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| /Documentation/devicetree/bindings/pwm/ |
| D | brcm,iproc-pwm.yaml | 42 reg = <0x18031000 0x28>;
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| D | brcm,bcm7038-pwm.yaml | 39 reg = <0xf0408000 0x28>;
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| D | pwm-bcm2835.yaml | 39 reg = <0x2020c000 0x28>;
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| /Documentation/devicetree/bindings/iio/potentiometer/ |
| D | max5432.yaml | 39 #size-cells = <0>;
42 reg = <0x28>;
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| /Documentation/devicetree/bindings/spi/ |
| D | spi-orion.txt | 19 chip-select lines 0 through 7 respectively.
37 #size-cells = <0>;
38 cell-index = <0>;
39 reg = <0x10600 0x28>;
47 #size-cells = <0>;
48 cell-index = <0>;
49 reg = <MBUS_ID(0xf0, 0x01) 0x10600 0x28>, /* control */
50 <MBUS_ID(0x01, 0x1e) 0 0xffffffff>, /* CS0 */
51 <MBUS_ID(0x01, 0x5e) 0 0xffffffff>, /* CS1 */
52 <MBUS_ID(0x01, 0x9e) 0 0xffffffff>, /* CS2 */
[all …]
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| D | nxp,sc18is.yaml | 43 #size-cells = <0>;
47 reg = <0x28>;
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| /Documentation/devicetree/bindings/clock/ |
| D | sunplus,sp7021-clkc.yaml | 38 #clock-cells = <0>;
45 reg = <0x9c000004 0x28>,
46 <0x9c000200 0x44>,
47 <0x9c000268 0x08>;
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| /Documentation/devicetree/bindings/iio/adc/ |
| D | cirrus,ep9301-adc.yaml | 42 reg = <0x80900000 0x28>;
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| /Documentation/devicetree/bindings/serial/ |
| D | sunplus,sp7021-uart.yaml | 50 reg = <0x9c000900 0x80>;
53 clocks = <&clkc 0x28>;
54 resets = <&rstc 0x18>;
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| /Documentation/devicetree/bindings/gpio/ |
| D | gpio-ts4900.txt | 25 reg = <0x28>;
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| /Documentation/devicetree/bindings/iio/proximity/ |
| D | semtech,sx9500.yaml | 40 #size-cells = <0>;
44 reg = <0x28>;
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