Searched +full:0 +full:x2800 (Results 1 – 5 of 5) sorted by relevance
| /Documentation/devicetree/bindings/power/supply/ |
| D | qcom,pm8941-coincell.yaml | 59 #size-cells = <0>; 63 reg = <0x2800>;
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| /Documentation/devicetree/bindings/pci/ |
| D | hisilicon,kirin-pcie.yaml | 78 reg = <0x0 0xf4000000 0x0 0x1000>, 79 <0x0 0xff3fe000 0x0 0x1000>, 80 <0x0 0xf3f20000 0x0 0x40000>, 81 <0x0 0xf5000000 0x0 0x2000>; 83 bus-range = <0x0 0xff>; 87 ranges = <0x02000000 0x0 0x00000000 88 0x0 0xf6000000 89 0x0 0x02000000>; 92 interrupts = <0 283 4>; 94 interrupt-map-mask = <0xf800 0 0 7>; [all …]
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| D | mvebu-pci.txt | 23 0x82000000 0 r MBUS_ID(0xf0, 0x01) r 0 s 32 registers area. This range entry translates the '0x82000000 0 r' PCI 33 address into the 'MBUS_ID(0xf0, 0x01) r' CPU address, which is part 34 of the internal register window (as identified by MBUS_ID(0xf0, 35 0x01)). 39 0x8t000000 s 0 MBUS_ID(w, a) 0 1 0 79 value is 0. 99 bus-range = <0x00 0xff>; 103 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */ 104 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */ [all …]
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| /Documentation/devicetree/bindings/display/msm/ |
| D | qcom,sm8450-mdss.yaml | 39 "^display-controller@[0-9a-f]+$": 47 "^displayport-controller@[0-9a-f]+$": 57 "^dsi@[0-9a-f]+$": 67 "^phy@[0-9a-f]+$": 91 reg = <0x0ae00000 0x1000>; 115 iommus = <&apps_smmu 0x2800 0x402>; 123 reg = <0x0ae01000 0x8f000>, 124 <0x0aeb0000 0x2008>; 147 interrupts = <0>; 151 #size-cells = <0>; [all …]
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| /Documentation/driver-api/media/drivers/ |
| D | cx2341x-devel.rst | 23 ivtvctl -O min=0x02000000,max=0x020000ff 32 (Base Address Register 0). The addresses here are offsets relative to the 37 0x00000000-0x00ffffff Encoder memory space 38 0x00000000-0x0003ffff Encode.rom 44 0x01000000-0x01ffffff Decoder memory space 45 0x01000000-0x0103ffff Decode.rom 47 0x0114b000-0x0115afff Audio.rom (deprecated?) 49 0x02000000-0x0200ffff Register Space 54 The registers occupy the 64k space starting at the 0x02000000 offset from BAR0. 59 DMA Registers 0x000-0xff: [all …]
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