Searched +full:0 +full:x28000000 (Results 1 – 8 of 8) sorted by relevance
| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | riscv,imsics.yaml | 36 XLEN-1 > (HART Index MSB) 12 0
39 |xxxxxx|Group Index|xxxxxxxxxxx|HART Index|Guest Index| 0 |
62 const: 0
67 const: 0
95 minimum: 0
97 default: 0
102 minimum: 0
109 minimum: 0
111 default: 0
117 minimum: 0
[all …]
|
| /Documentation/devicetree/bindings/net/ |
| D | toshiba,visconti-dwmac.yaml | 64 reg = <0 0x28000000 0 0x10000>;
76 #address-cells = <0x1>;
77 #size-cells = <0x0>;
82 reg = <0x1>;
|
| /Documentation/devicetree/bindings/clock/ |
| D | qcom,lcc.yaml | 117 reg = <0x28000000 0x1000>;
|
| /Documentation/devicetree/bindings/arm/ |
| D | arm,coresight-stm.yaml | 90 reg = <0x20100000 0x1000>,
91 <0x28000000 0x180000>;
|
| /Documentation/devicetree/bindings/pci/ |
| D | brcm,iproc-pcie.yaml | 117 reg = <0x18012000 0x1000>;
120 interrupt-map-mask = <0 0 0 0>;
121 interrupt-map = <0 0 0 0 &gic GIC_SPI 100 IRQ_TYPE_NONE>;
123 linux,pci-domain = <0>;
125 bus-range = <0x00 0xff>;
130 ranges = <0x81000000 0 0 0x28000000 0 0x00010000>,
131 <0x82000000 0 0x20000000 0x20000000 0 0x04000000>;
133 phys = <&phy 0 5>;
137 brcm,pcie-ob-axi-offset = <0x00000000>;
155 reg = <0x18013000 0x1000>;
[all …]
|
| D | mediatek-pcie.txt | 32 where N starting from 0 to one less than the number of root ports.
80 reg = <0 0x1a000000 0 0x1000>;
88 reg = <0 0x1a140000 0 0x1000>, /* PCIe shared registers */
89 <0 0x1a142000 0 0x1000>, /* Port0 registers */
90 <0 0x1a143000 0 0x1000>, /* Port1 registers */
91 <0 0x1a144000 0 0x1000>; /* Port2 registers */
96 interrupt-map-mask = <0xf800 0 0 0>;
97 interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,
98 <0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>,
99 <0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
[all …]
|
| D | nvidia,tegra20-pcie.txt | 27 - cell 0 specifies the bus and device numbers of the root port:
30 - cell 1 denotes the upper 32 address bits and should be 0
45 - 0x81000000: I/O memory region
46 - 0x82000000: non-prefetchable memory region
47 - 0xc2000000: prefetchable memory region
73 - pinctrl-0: phandle for the default/active state of pin configurations.
104 - If lanes 0 to 3 are used:
150 - Root port 0 uses 4 lanes, root port 1 is unused.
158 "pcie-N": where N ranges from 0 to the value specified in nvidia,num-lanes.
171 reg = <0x80003000 0x00000800 /* PADS registers */
[all …]
|
| D | nvidia,tegra194-pcie.yaml | 85 - const: p2u-0
123 0: C0
132 0 : C0
260 bus@0 {
263 ranges = <0x0 0x0 0x0 0x8 0x0>;
268 reg = <0x0 0x14180000 0x0 0x00020000>, /* appl registers (128K) */
269 <0x0 0x38000000 0x0 0x00040000>, /* configuration space (256K) */
270 <0x0 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
271 <0x0 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */
278 linux,pci-domain = <0>;
[all …]
|