Searched +full:0 +full:x2d000000 (Results 1 – 2 of 2) sorted by relevance
| /Documentation/devicetree/bindings/media/ |
| D | amphion,vpu.yaml | 20 pattern: "^vpu@[0-9a-f]+$"
43 "^mailbox@[0-9a-f]+$":
50 "^vpu-core@[0-9a-f]+$":
116 ranges = <0x2c000000 0x2c000000 0x2000000>;
117 reg = <0x2c000000 0x1000000>;
124 reg = <0x2d000000 0x20000>;
125 interrupts = <0 472 4>;
132 reg = <0x2d020000 0x20000>;
133 interrupts = <0 473 4>;
140 reg = <0x2d040000 0x20000>;
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | arm,gic-v3.yaml | 33 enum: [ 0, 1, 2 ]
46 The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI
51 SPI interrupts are in the range [0-987]. PPI interrupts are in the
52 range [0-15]. Extended SPI interrupts are in the range [0-1023].
53 Extended PPI interrupts are in the range [0-127].
56 bits[3:0] trigger type and level flags.
68 of 0 if present.
83 ARMv8.0 architecture such as Cortex-A32, A34, A35, A53, A57, A72 and
99 multipleOf: 0x10000
100 exclusiveMinimum: 0
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