Searched +full:0 +full:x3 (Results 1 – 25 of 136) sorted by relevance
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| /Documentation/devicetree/bindings/soc/ti/ |
| D | ti,j721e-system-controller.yaml | 48 "^mux-controller@[0-9a-f]+$":
53 "^clock-controller@[0-9a-f]+$":
59 "phy@[0-9a-f]+$":
65 "^chipid@[0-9a-f]+$":
84 reg = <0x00100000 0x1c000>;
91 reg = <0x00004080 0x50>;
95 <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
96 <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */
97 <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */
98 <0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */
[all …]
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| D | ti,am654-serdes-ctrl.yaml | 36 reg = <0x4080 0x4>;
41 mux-reg-masks = <0x0 0x3>; /* lane select */
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| /Documentation/devicetree/bindings/dma/stm32/ |
| D | st,stm32-mdma.yaml | 17 0x0: Low
18 0x1: Medium
19 0x2: High
20 0x3: Very high
22 -bit 0-1: Source increment mode
23 0x0: Source address pointer is fixed
24 0x2: Source address pointer is incremented after each data transfer
25 0x3: Source address pointer is decremented after each data transfer
27 0x0: Destination address pointer is fixed
28 0x2: Destination address pointer is incremented after each data transfer
[all …]
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| D | st,stm32-dma.yaml | 20 0x0: no address increment between transfers
21 0x1: increment address between transfers
23 0x0: no address increment between transfers
24 0x1: increment address between transfers
26 0x0: offset size is linked to the peripheral bus width
27 0x1: offset size is fixed to 4 (32-bit alignment)
29 0x0: low
30 0x1: medium
31 0x2: high
32 0x3: very high
[all …]
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| /Documentation/devicetree/bindings/iio/light/ |
| D | ti,opt4001.yaml | 15 Picostar is a 4 pinned SMT and sot-5x3 is a 8 pinned SOT.
22 - ti,opt4001-sot-5x3
42 const: ti,opt4001-sot-5x3
58 #size-cells = <0>;
61 compatible = "ti,opt4001-sot-5x3";
62 reg = <0x44>;
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| /Documentation/devicetree/bindings/pinctrl/ |
| D | fsl,imx8ulp-pinctrl.yaml | 73 reg = <0x298c0000 0x10000>;
77 <0x0138 0x08F0 0x4 0x3 0x3>,
78 <0x013C 0x08EC 0x4 0x3 0x3>;
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| /Documentation/devicetree/bindings/regulator/ |
| D | qcom-labibb-regulator.yaml | 89 interrupts = <0x3 0xde 0x1 IRQ_TYPE_EDGE_RISING>,
90 <0x3 0xde 0x0 IRQ_TYPE_LEVEL_LOW>;
95 interrupts = <0x3 0xdc 0x2 IRQ_TYPE_EDGE_RISING>,
96 <0x3 0xdc 0x0 IRQ_TYPE_LEVEL_LOW>;
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| /Documentation/input/devices/ |
| D | alps.rst | 32 E8-E6-E6-E6-E9. An ALPS touchpad should respond with either 00-00-0A or
33 00-00-64 if no buttons are pressed. The bits 0-2 of the first byte will be 1s
45 The new ALPS touchpads have an E7 signature of 73-03-50 or 73-03-0A but
94 byte 0: 0 0 YSGN XSGN 1 M R L
95 byte 1: X7 X6 X5 X4 X3 X2 X1 X0
109 byte 0: 1 0 0 0 1 x9 x8 x7
110 byte 1: 0 x6 x5 x4 x3 x2 x1 x0
111 byte 2: 0 ? ? l r ? fin ges
112 byte 3: 0 ? ? ? ? y9 y8 y7
113 byte 4: 0 y6 y5 y4 y3 y2 y1 y0
[all …]
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| /Documentation/devicetree/bindings/pci/ |
| D | rockchip-dw-pcie.yaml | 50 const: 0
89 reg = <0x3 0xc0800000 0x0 0x390000>,
90 <0x0 0xfe280000 0x0 0x10000>,
91 <0x3 0x80000000 0x0 0x100000>;
93 bus-range = <0x20 0x2f>;
109 msi-map = <0x2000 &its 0x2000 0x1000>;
114 ranges = <0x81000000 0x0 0x80800000 0x3 0x80800000 0x0 0x100000>,
115 <0x83000000 0x0 0x80900000 0x3 0x80900000 0x0 0x3f700000>;
123 #address-cells = <0>;
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| D | 83xx-512x-pci.txt | 12 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
14 /* IDSEL 0x0E -mini PCI */
15 0x7000 0x0 0x0 0x1 &ipic 18 0x8
16 0x7000 0x0 0x0 0x2 &ipic 18 0x8
17 0x7000 0x0 0x0 0x3 &ipic 18 0x8
18 0x7000 0x0 0x0 0x4 &ipic 18 0x8
20 /* IDSEL 0x0F - PCI slot */
21 0x7800 0x0 0x0 0x1 &ipic 17 0x8
22 0x7800 0x0 0x0 0x2 &ipic 18 0x8
23 0x7800 0x0 0x0 0x3 &ipic 17 0x8
[all …]
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| D | starfive,jh7110-pcie.yaml | 81 reg = <0x9 0x40000000 0x0 0x10000000>,
82 <0x0 0x2b000000 0x0 0x1000000>;
88 ranges = <0x82000000 0x0 0x30000000 0x0 0x30000000 0x0 0x08000000>,
89 <0xc3000000 0x9 0x00000000 0x9 0x00000000 0x0 0x40000000>;
91 bus-range = <0x0 0xff>;
94 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
95 interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc0 0x1>,
96 <0x0 0x0 0x0 0x2 &pcie_intc0 0x2>,
97 <0x0 0x0 0x0 0x3 &pcie_intc0 0x3>,
98 <0x0 0x0 0x0 0x4 &pcie_intc0 0x4>;
[all …]
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| /Documentation/devicetree/bindings/mux/ |
| D | reg-mux.yaml | 54 <0x54 0xf8>, /* 0: reg 0x54, bits 7:3 */
55 <0x54 0x07>; /* 1: reg 0x54, bits 2:0 */
60 mux-controls = <&mux1 0>;
63 #size-cells = <0>;
65 mdio@0 {
66 reg = <0x0>;
68 #size-cells = <0>;
72 reg = <0x8>;
74 #size-cells = <0>;
83 #size-cells = <0>;
[all …]
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| /Documentation/devicetree/bindings/goldfish/ |
| D | battery.txt | 15 reg = <0x9020000 0x1000>;
16 interrupts = <0x3>;
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| /Documentation/devicetree/bindings/gpio/ |
| D | gpio-stp-xway.yaml | 20 pattern: "^gpio@[0-9a-f]+$"
41 minimum: 0x000000
42 maximum: 0xffffff
49 minimum: 0x0
50 maximum: 0x7
57 minimum: 0x0
58 maximum: 0x3
71 minimum: 0x0
72 maximum: 0x7
86 reg = <0xE100BB0 0x40>;
[all …]
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| /Documentation/arch/powerpc/ |
| D | ptrace.rst | 44 #define PPC_DEBUG_FEATURE_INSN_BP_RANGE 0x1
45 #define PPC_DEBUG_FEATURE_INSN_BP_MASK 0x2
46 #define PPC_DEBUG_FEATURE_DATA_BP_RANGE 0x4
47 #define PPC_DEBUG_FEATURE_DATA_BP_MASK 0x8
48 #define PPC_DEBUG_FEATURE_DATA_BP_DAWR 0x10
49 #define PPC_DEBUG_FEATURE_DATA_BP_ARCH_31 0x20
57 #define PPC_BREAKPOINT_TRIGGER_EXECUTE 0x1
58 #define PPC_BREAKPOINT_TRIGGER_READ 0x2
59 #define PPC_BREAKPOINT_TRIGGER_WRITE 0x4
61 #define PPC_BREAKPOINT_MODE_EXACT 0x0
[all …]
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| /Documentation/devicetree/bindings/sound/ |
| D | cs35l33.txt | 22 0, then VBST = VP. If greater than 0, the boost voltage will be 3300mV with
31 20ms. If this property is set to 0,1,2,3 then ramp times would be 40ms,
39 ADC data word. This property can be set as a value of 0 for bits 15 down
40 to 0, 6 for 21 down to 6, 7, for 22 down to 7, 8 for 23 down to 8.
54 LRCLK cycles. If this property is set to 0, 1, 2, or 3 then the memory
64 0xF).
72 from 0 to 7 for delays of 5ms, 10ms, 50ms, 100ms, 200ms, 500ms, 1000ms.
80 The reference voltage starts at 3000mV with a value of 0x3 and is increased
85 tracking. This property can be set to values from 0 to 3 with rates of 128
90 using VPMON. This property can be set to values from 0 to 6 starting at
[all …]
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| /Documentation/ABI/testing/ |
| D | debugfs-iio-backend | 13 Reading address 0x50
14 echo 0x50 > direct_reg_access
17 Writing address 0x50
18 echo 0x50 0x3 > direct_reg_access
19 //readback address 0x50
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| D | sysfs-bus-iio-mpu6050 | 4 KernelVersion: 3.4.0
8 is a 3x3 unitary matrix. A typical mounting matrix would look like
9 [0, 1, 0; 1, 0, 0; 0, 0, -1]. Using this information, it would be
12 [1, 0, 0; 0, 1, 0; 0, 0, 1] means sensor chip and device are perfectly
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| D | sysfs-class-extcon | 46 HDMI=0
48 EAR_JACK=0
55 state number starting with 0x::
57 # echo 0xHEX > state
73 "X" (integer between 0 and 31) of an extcon device.
80 state of cable "X" (integer between 0 and 31) of an extcon
81 device. The state value is either 0 (detached) or 1
90 {0x3, 0x5, 0xC, 0x0}, then the output is::
93 0x3
94 0x5
[all …]
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| /Documentation/gpu/amdgpu/ |
| D | debugging.rst | 11 `vm_fault_stop` - If non-0, halt the GPU memory controller on a GPU page fault.
13 `vm_update_mode` - If non-0, use the CPU to update GPU page tables rather than
26 …[gfxhub0] no-retry page fault (src_id:0 ring:24 vmid:3 pasid:32777, for process glxinfo pid 2424 t…
27 in page starting at address 0x0000800102800000 from IH client 0x1b (UTCL2)
28 VM_L2_PROTECTION_FAULT_STATUS:0x00301030
29 Faulty UTCL2 client ID: TCP (0x8)
30 MORE_FAULTS: 0x0
31 WALKER_ERROR: 0x0
32 PERMISSION_FAULTS: 0x3
33 MAPPING_ERROR: 0x0
[all …]
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| /Documentation/devicetree/bindings/cache/ |
| D | marvell,tauros2-cache.txt | 8 CACHE_TAUROS2_PREFETCH_ON (1 << 0)
16 marvell,tauros2-cache-features = <0x3>;
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| /Documentation/devicetree/bindings/ata/ |
| D | baikal,bt1-ahci.yaml | 46 maximum: 0x3
49 "^sata-port@[0-1]$":
54 minimum: 0
61 transaction size can't exceed 16 beats (AxLEN[3:0]).
68 transaction size can't exceed 16 beats (AxLEN[3:0]).
87 reg = <0x1f050000 0x2000>;
89 #size-cells = <0>;
91 interrupts = <0 64 4>;
96 resets = <&ccu_axi 2>, <&ccu_sys 0>;
99 ports-implemented = <0x3>;
[all …]
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| /Documentation/devicetree/bindings/net/dsa/ |
| D | qca,ar9331.yaml | 38 '(ethernet-)?phy@[0-4]+$':
74 #size-cells = <0>;
78 reg = <0x10>;
90 #size-cells = <0>;
92 port@0 {
93 reg = <0x0>;
105 reg = <0x1>;
111 reg = <0x2>;
117 reg = <0x3>;
123 reg = <0x4>;
[all …]
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| /Documentation/devicetree/bindings/leds/ |
| D | leds-lp50xx.yaml | 38 lp5009/12 - 0x14, 0x15, 0x16, 0x17
39 lp5018/24 - 0x28, 0x29, 0x2a, 0x2b
40 lp5030/36 - 0x30, 0x31, 0x32, 0x33
53 const: 0
56 '^multi-led@[0-9a-f]$':
74 const: 0
77 "^led@[0-9a-f]+$":
102 #size-cells = <0>;
106 reg = <0x14>;
108 #size-cells = <0>;
[all …]
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| /Documentation/devicetree/bindings/net/ |
| D | apm-xgene-mdio.txt | 8 - #size-cells: Must be <0>.
21 #size-cells = <0>;
22 reg = <0x0 0x17020000 0x0 0xd100>;
23 clocks = <&menetclk 0>;
29 reg = <0x3>;
32 reg = <0x4>;
35 reg = <0x5>;
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