Searched +full:0 +full:x3c (Results 1 – 25 of 48) sorted by relevance
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| /Documentation/devicetree/bindings/thermal/ |
| D | ti_soc_thermal.txt | 32 reg = <0x48002524 0x4>;
38 reg = <0x48002524 0x4>;
44 reg = <0x4a002260 0x4 0x4a00232C 0x4>;
50 reg = <0x4a002260 0x4
51 0x4a00232C 0x4
52 0x4a002378 0x18>;
54 interrupts = <0 126 4>; /* talert */
55 gpios = <&gpio3 22 0>; /* tshut */
60 reg = <0x4a002260 0x4
61 0x4a00232C 0x4
[all …]
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| /Documentation/devicetree/bindings/media/i2c/ |
| D | galaxycore,gc2145.yaml | 29 const: 0x3c
91 #size-cells = <0>;
95 reg = <0x3c>;
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| D | ovti,ov5640.yaml | 59 const: 0
71 enum: [0, 2]
92 #size-cells = <0>;
97 pinctrl-0 = <&pinctrl_ov5640>;
98 reg = <0x3c>;
112 clock-lanes = <0>;
122 #size-cells = <0>;
127 pinctrl-0 = <&pinctrl_ov5640>;
128 reg = <0x3c>;
141 hsync-active = <0>;
[all …]
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| D | alliedvision,alvium-csi2.yaml | 64 #size-cells = <0>;
68 reg = <0x3c>;
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| D | ovti,ov2685.yaml | 77 #size-cells = <0>;
81 reg = <0x3c>;
83 pinctrl-0 = <&clk_24m_cam>;
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| D | ovti,ov7251.yaml | 87 #size-cells = <0>;
91 reg = <0x3c>;
103 data-lanes = <0>;
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| D | ovti,ov5645.yaml | 81 #size-cells = <0>;
85 reg = <0x3c>;
94 pinctrl-0 = <&pinctrl_ov5645>;
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| D | ovti,ov5642.yaml | 61 enum: [0, 2]
62 default: 0
65 enum: [0, 1]
69 enum: [0, 1]
73 enum: [0, 1]
93 const: 0
115 #size-cells = <0>;
119 reg = <0x3c>;
121 pinctrl-0 = <&pinctrl_ov5642>;
135 hsync-active = <0>;
[all …]
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| /Documentation/devicetree/bindings/usb/ |
| D | isp1301.txt | 15 reg = <0x2c>;
20 reg = <0x31020000 0x300>;
22 interrupts = <0x3d 0>, <0x3e 0>, <0x3c 0>, <0x3a 0>;
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| D | lpc32xx-udc.txt | 19 reg = <0x2c>;
24 reg = <0x31020000 0x300>;
26 interrupts = <0x3d 0>, <0x3e 0>, <0x3c 0>, <0x3a 0>;
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| /Documentation/devicetree/bindings/rtc/ |
| D | marvell,pxa-rtc.yaml | 38 reg = <0x40900000 0x3c>;
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| /Documentation/devicetree/bindings/phy/ |
| D | ingenic,phy-usb.yaml | 36 const: 0
52 reg = <0x3c 0x10>;
57 #phy-cells = <0>;
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| /Documentation/devicetree/bindings/timer/ |
| D | ingenic,sysost.yaml | 53 reg = <0x12000000 0x3c>;
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| /Documentation/devicetree/bindings/hwmon/ |
| D | amd,sbrmi.yaml | 31 socket 0 and 70h for socket 1, but it could vary based on hardware
46 #size-cells = <0>;
50 reg = <0x3c>;
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| /Documentation/devicetree/bindings/dma/stm32/ |
| D | st,stm32-dmamux.yaml | 49 reg = <0x40020800 0x3c>;
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| /Documentation/devicetree/bindings/sound/ |
| D | adi,adau1372.yaml | 29 const: 0
54 #size-cells = <0>;
57 reg = <0x3c>;
58 #sound-dai-cells = <0>;
66 #clock-cells = <0>;
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| /Documentation/devicetree/bindings/leds/ |
| D | leds-is31fl32xx.txt | 17 - size-cells : must be 0
31 reg = <0x3c>;
33 #size-cells = <0>;
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| /Documentation/devicetree/bindings/display/ |
| D | solomon,ssd132x.yaml | 68 #size-cells = <0>;
72 reg = <0x3c>;
80 #size-cells = <0>;
82 oled@0 {
84 reg = <0x0>;
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| /Documentation/devicetree/bindings/regulator/ |
| D | max8907.txt | 34 reg = <0x3c>;
35 interrupts = <0 86 0x4>;
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| /Documentation/devicetree/bindings/mux/ |
| D | gpio-mux.yaml | 18 bit. An active pin is a binary 1, an inactive pin is a binary 0.
29 enum: [ 0, 1 ]
54 #mux-control-cells = <0>;
56 mux-gpios = <&pioA 0 GPIO_ACTIVE_HIGH>,
62 io-channels = <&adc 0>;
77 #size-cells = <0>;
79 i2c@0 {
80 reg = <0>;
82 #size-cells = <0>;
85 reg = <0x3c>;
[all …]
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| /Documentation/devicetree/bindings/net/ |
| D | rockchip,emac.yaml | 96 reg = <0xc0fc2000 0x3c>;
101 pinctrl-0 = <&emac_xfer>, <&emac_mdio>, <&phy_int>;
109 #size-cells = <0>;
111 phy0: ethernet-phy@0 {
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| /Documentation/devicetree/bindings/arm/bcm/ |
| D | brcm,bcm63138.txt | 32 cpu@0 {
34 reg = <0>;
50 reg = <0x8000 0x50>;
69 - offset: Should be 0x34 to denote the offset of the TIMER_WD_TIMER_RESET register
77 reg = <0x80 0x3c>;
83 offset = <0x34>;
84 mask = <0x1>;
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| /Documentation/devicetree/bindings/ipmi/ |
| D | aspeed,ast2400-kcs-bmc.yaml | 102 reg = <0x24 0x1>, <0x30 0x1>, <0x3c 0x1>;
103 aspeed,lpc-io-reg = <0xca2>;
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| /Documentation/devicetree/bindings/mips/lantiq/ |
| D | rcu.txt | 25 reg = <0x203000 0x100>;
26 ranges = <0x0 0x203000 0x100>;
31 reg = <0x10 4>, <0x14 4>;
38 reg = <0x48 4>, <0x24 4>;
45 reg = <0x18 4>, <0x38 4>;
49 #phy-cells = <0>;
54 reg = <0x34 4>, <0x3C 4>;
58 #phy-cells = <0>;
63 reg = <0x10 4>;
66 offset = <0x10>;
[all …]
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| /Documentation/devicetree/bindings/clock/ |
| D | ingenic,cgu.yaml | 37 pattern: "^clock-controller@[0-9a-f]+$"
112 reg = <0x10000000 0x100>;
115 ranges = <0x0 0x10000000 0x100>;
124 reg = <0x3c 0x10>;
130 #phy-cells = <0>;
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