Searched +full:0 +full:x4080 (Results 1 – 3 of 3) sorted by relevance
| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | riscv,aplic.yaml | 74 first child APLIC domain assigned child index 0. The APLIC domain child
122 reg = <0xc000000 0x4080>;
134 reg = <0xd000000 0x4080>;
144 reg = <0xe000000 0x4080>;
156 reg = <0xc000000 0x4000>;
167 reg = <0xd000000 0x4000>;
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| /Documentation/devicetree/bindings/soc/ti/ |
| D | ti,am654-serdes-ctrl.yaml | 36 reg = <0x4080 0x4>;
41 mux-reg-masks = <0x0 0x3>; /* lane select */
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| D | ti,j721e-system-controller.yaml | 48 "^mux-controller@[0-9a-f]+$":
53 "^clock-controller@[0-9a-f]+$":
59 "phy@[0-9a-f]+$":
65 "^chipid@[0-9a-f]+$":
84 reg = <0x00100000 0x1c000>;
91 reg = <0x00004080 0x50>;
95 <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
96 <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */
97 <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */
98 <0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */
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