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/Documentation/devicetree/bindings/sound/
Dtas2552.txt8 - reg - I2C slave address: it can be 0x40 if ADDR pin is 0
9 or 0x41 if ADDR pin is 1.
28 reg = <0x41>;
Dti,tas2770.yaml30 I2C address of the device can be between 0x41 to 0x48.
56 - 0 # Rising edge
62 enum: [0, 1]
75 #size-cells = <0>;
78 reg = <0x41>;
79 #sound-dai-cells = <0>;
82 reset-gpio = <&gpio1 15 0>;
83 shutdown-gpios = <&gpio1 14 0>;
84 ti,imon-slot-no = <0>;
Dcs35l32.txt8 of the AD0 pin. Level 0 is 0x40 while Level 1 is 0x41.
19 0 = Automatically managed. Boost-converter output voltage is the higher
29 0 = Left/right channels VMON[11:0], IMON[11:0], VPMON[7:0].
30 1 = Left/right channels VMON[11:0], IMON[11:0], STATUS.
31 2 = (Default) left/right channels VMON[15:0], IMON [15:0].
32 3 = Left/right channels VPMON[7:0], STATUS.
36 0 = (Default) One IC.
40 0 = 3.1V
46 0 = 3.1V
57 reg = <0x40>;
[all …]
/Documentation/devicetree/bindings/input/
Dilitek,ili9882t.yaml24 const: 0x41
54 #size-cells = <0>;
58 reg = <0x41>;
Dilitek,ili2901.yaml54 #size-cells = <0>;
58 reg = <0x41>;
Dmicrochip,qt1050.txt26 - reg: The key number. Valid values: 0, 1, 2, 3, 4.
36 Valid value range: 0 - 637500; values must be a multiple of 2500;
37 default is 0.
46 Valid value range: 0 - 255; default is 20.
53 reg = <0x41>;
57 up@0 {
58 reg = <0>;
/Documentation/devicetree/bindings/gpio/
Dgpio-adnp.txt9 - bit 0: polarity (0: normal, 1: inverted)
21 reg = <0x41>;
/Documentation/devicetree/bindings/pwm/
Dnxp,pca9685-pwm.txt24 reg = <0x41>;
/Documentation/devicetree/bindings/input/touchscreen/
Dbu21029.txt5 - reg : i2c device address of the chip (0x40 or 0x41)
24 reg = <0x40>;
Dilitek_ts_i2c.yaml64 #size-cells = <0>;
68 reg = <0x41>;
/Documentation/devicetree/bindings/regulator/
Dti,tps62870.yaml40 #size-cells = <0>;
44 reg = <0x41>;
/Documentation/devicetree/bindings/iio/temperature/
Dti,tmp007.yaml25 0 0 0x40
26 0 1 0x41
27 0 SDA 0x42
28 0 SCL 0x43
29 1 0 0x44
30 1 1 0x45
31 1 SDA 0x46
32 1 SCL 0x47
48 #size-cells = <0>;
52 reg = <0x40>;
[all …]
/Documentation/devicetree/bindings/media/i2c/
Dimi,rdacm2x-gmsl.yaml67 const: 0
104 #size-cells = <0>;
106 reg = <0 0xe66d8000>;
110 reg = <0x31>, <0x41>, <0x51>;
123 #size-cells = <0>;
125 reg = <0 0xe66d8000>;
129 reg = <0x31>, <0x41>;
/Documentation/devicetree/bindings/mfd/
Ddelta,tn48m-cpld.yaml35 const: 0
44 "^gpio(@[0-9a-f]+)?$":
56 #size-cells = <0>;
60 reg = <0x41>;
62 #size-cells = <0>;
66 reg = <0x31>;
73 reg = <0x3a>;
80 reg = <0x40>;
Dst,stmpe.yaml53 enum: [ 0, 1, 2, 3, 4, 5, 6 ]
56 0 = 36 clock ticks
66 enum: [ 0, 1 ]
67 description: ADC bit mode 0 = 10bit ADC, 1 = 12bit ADC
71 enum: [ 0, 1 ]
72 description: ADC reference source 0 = internal, 1 = external
76 enum: [ 0, 1, 2, 3 ]
79 0 = 1.625 MHz
142 enum: [ 0, 1, 2, 3 ]
145 0 = 1 sample
[all …]
/Documentation/devicetree/bindings/powerpc/fsl/
Draideng.txt11 - compatible: Should contain "fsl,raideng-v1.0" as the value
13 major number whereas 0 represents minor number. The
22 compatible = "fsl,raideng-v1.0";
25 reg = <0x320000 0x10000>;
26 ranges = <0 0x320000 0x10000>;
33 - compatible: Should contain "fsl,raideng-v1.0-job-queue" as the value
42 compatible = "fsl,raideng-v1.0-job-queue";
43 reg = <0x1000 0x1000>;
44 ranges = <0x0 0x1000 0x1000>;
51 - compatible: Must contain "fsl,raideng-v1.0-job-ring" as the value
[all …]
/Documentation/devicetree/bindings/soc/fsl/
Dfsl,qman-portal.yaml25 - fsl,qman-portal-1.2.0
89 qman-portal@0 {
90 compatible = "fsl,qman-portal-1.2.0", "fsl,qman-portal";
91 reg = <0 0x4000>, <0x100000 0x1000>;
92 interrupts = <104 IRQ_TYPE_EDGE_FALLING 0 0>;
94 fsl,qman-channel-id = <0>;
97 fsl,liodn = <0x21>;
102 fsl,liodn = <0xa1>;
107 fsl,liodn = <0x41 0x66>;
/Documentation/devicetree/bindings/leds/backlight/
Dlp855x-backlight.yaml61 "^rom-[0-9a-f]{2}h$":
85 #size-cells = <0>;
89 reg = <0x2c>;
91 dev-ctrl = /bits/ 8 <0x00>;
93 pwms = <&pwm 0 10000>;
98 rom-addr = /bits/ 8 <0x14>;
99 rom-val = /bits/ 8 <0xcf>;
104 rom-addr = /bits/ 8 <0x15>;
105 rom-val = /bits/ 8 <0xc7>;
110 rom-addr = /bits/ 8 <0x19>;
[all …]
/Documentation/devicetree/bindings/interrupt-controller/
Dinterrupts.txt17 interrupts = <5 0>, <6 0>;
31 interrupts-extended = <&intc1 5 1>, <&intc2 1 0>;
55 reg = <0x10140000 0x1000>;
62 reg = <0x10003000 0x1000>;
72 - bits[3:0] trigger type and level flags
83 reg = <0x41>;
99 reg = <0x2b>;
102 interrupts = <3 0x8>;
105 #size-cells = <0>;
107 threshold = <0x40>;
/Documentation/admin-guide/perf/
Dimx-ddr.rst11 is one register for each counter. Counter 0 is special in that it always counts
28 AXI filtering is only used by CSV modes 0x41 (axid-read) and 0x42 (axid-write)
32 type of AXI filter (filter, enhanced_filter and super_filter). Value 0 for
35 * With DDR_CAP_AXI_ID_FILTER quirk(filter: 1, enhanced_filter: 0, super_filter: 0).
40 - 0: corresponding bit is masked.
54 perf stat -a -e imx8_ddr0/axid-read,axi_mask=0xMMMM,axi_id=0xDDDD/ cmd
55 perf stat -a -e imx8_ddr0/axid-write,axi_mask=0xMMMM,axi_id=0xDDDD/ cmd
65 perf stat -a -e imx8_ddr0/axid-read,axi_id=0x12/ cmd, which will monitor ARID=0x12
67 * With DDR_CAP_AXI_ID_FILTER_ENHANCED quirk(filter: 1, enhanced_filter: 1, super_filter: 0).
72 * With DDR_CAP_AXI_ID_PORT_CHANNEL_FILTER quirk(filter: 0, enhanced_filter: 0, super_filter: 1).
[all …]
/Documentation/translations/zh_CN/dev-tools/
Dkmemleak.rst59 设定自动内存扫描间隔，以秒为单位（默认值为 600，设置为 0 表示停
213 unreferenced object 0xffff89862ca702e8 (size 32):
219 [<00000000e0a73ec7>] 0xffffffffc01d2036
220 [<000000000c5d2a46>] do_one_initcall+0x41/0x1df
221 [<0000000046db7e0a>] do_init_module+0x55/0x200
222 [<00000000542b9814>] load_module+0x203c/0x2480
223 [<00000000c2850256>] __do_sys_finit_module+0xba/0xe0
224 [<000000006564e7ef>] do_syscall_64+0x43/0x110
225 [<000000007c873fa6>] entry_SYSCALL_64_after_hwframe+0x44/0xa9
/Documentation/virt/kvm/x86/
Dtimekeeping.rst53 The PIT uses I/O ports 0x40 - 0x43. Access to the 16-bit counters is done
57 controlled by port 61h, bit 0, as illustrated in the following diagram::
61 | 1.1932 MHz|---------->| CLOCK OUT | ---------> IRQ 0
63 -------------- | +->| GATE TIMER 0 |
77 Port 61h, bit 0 -------->| GATE TIMER 2 | \_.---- ____
84 Mode 0: Single Timeout.
86 when the gate is high (always true for timers 0 and 1). When the count
128 command port, 0x43 is used to set the counter and mode for each of the three
131 PIT commands, issued to port 0x43, using the following bit encoding::
134 Bit 3-1: Mode (000 = Mode 0, 101 = Mode 5, 11X = undefined)
[all …]
/Documentation/PCI/
Dboot-interrupts.rst38 CPU: 0 PID: 2988 Comm: irq/34-nipalk Tainted: 4.14.87-rt49-02410-g4a640ec-dirty #1
43 ? dump_stack+0x46/0x5e
44 ? __report_bad_irq+0x2e/0xb0
45 ? note_interrupt+0x242/0x290
46 ? nNIKAL100_memoryRead16+0x8/0x10 [nikal]
47 ? handle_irq_event_percpu+0x55/0x70
48 ? handle_irq_event+0x4f/0x80
49 ? handle_fasteoi_irq+0x81/0x180
50 ? handle_irq+0x1c/0x30
51 ? do_IRQ+0x41/0xd0
[all …]
/Documentation/dev-tools/
Dkmemleak.rst56 (default 600, 0 to stop the automatic scanning)
242 unreferenced object 0xffff89862ca702e8 (size 32):
248 [<00000000e0a73ec7>] 0xffffffffc01d2036
249 [<000000000c5d2a46>] do_one_initcall+0x41/0x1df
250 [<0000000046db7e0a>] do_init_module+0x55/0x200
251 [<00000000542b9814>] load_module+0x203c/0x2480
252 [<00000000c2850256>] __do_sys_finit_module+0xba/0xe0
253 [<000000006564e7ef>] do_syscall_64+0x43/0x110
254 [<000000007c873fa6>] entry_SYSCALL_64_after_hwframe+0x44/0xa9
/Documentation/locking/
Dlockstat.rst56 - shortest (non-0) time we ever had to wait for a lock
69 - shortest (non-0) time we ever held the lock
97 # echo 0 >/proc/sys/kernel/lock_stat
114 … &mm->mmap_sem 1 [<ffffffff811502a7>] khugepaged_scan_mm_slot+0x57/0x280
115 … &mm->mmap_sem 96 [<ffffffff815351c4>] __do_page_fault+0x1d4/0x510
116 … &mm->mmap_sem 34 [<ffffffff81113d77>] vm_mmap_pgoff+0x87/0xd0
117 … &mm->mmap_sem 17 [<ffffffff81127e71>] vm_munmap+0x41/0x80
119 … &mm->mmap_sem 1 [<ffffffff81046fda>] dup_mmap+0x2a/0x3f0
120 … &mm->mmap_sem 60 [<ffffffff81129e29>] SyS_mprotect+0xe9/0x250
121 … &mm->mmap_sem 41 [<ffffffff815351c4>] __do_page_fault+0x1d4/0x510
[all …]

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