Searched +full:0 +full:x5 (Results 1 – 25 of 54) sorted by relevance
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| /Documentation/input/devices/ |
| D | alps.rst | 32 E8-E6-E6-E6-E9. An ALPS touchpad should respond with either 00-00-0A or
33 00-00-64 if no buttons are pressed. The bits 0-2 of the first byte will be 1s
45 The new ALPS touchpads have an E7 signature of 73-03-50 or 73-03-0A but
94 byte 0: 0 0 YSGN XSGN 1 M R L
95 byte 1: X7 X6 X5 X4 X3 X2 X1 X0
109 byte 0: 1 0 0 0 1 x9 x8 x7
110 byte 1: 0 x6 x5 x4 x3 x2 x1 x0
111 byte 2: 0 ? ? l r ? fin ges
112 byte 3: 0 ? ? ? ? y9 y8 y7
113 byte 4: 0 y6 y5 y4 y3 y2 y1 y0
[all …]
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| D | elantech.rst | 69 (TouchPadOff=0) will also disable the buttons associated with the touchpad.
99 By echoing "0" to this file all debugging will be turned OFF.
113 By echoing "0" to this file parity checking will be turned OFF. Any
128 Sets crc_enabled to 0/1. The name "crc_enabled" is the official name of
138 "0" or "1" to this file will set the state to "0" or "1".
143 To detect the hardware version, read the version number as param[0].param[1].param[2]::
164 Probably all the versions with param[0] <= 01 can be considered as
179 echo -n 0x16 > reg_10
183 bit 7 6 5 4 3 2 1 0
197 bit 7 6 5 4 3 2 1 0
[all …]
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| D | amijoy.rst | 96 JOY0DAT 00A R Denise Joystick-mouse 0 data (left vert, horiz)
116 JOY0DAT Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 X7 X6 X5 X4 X3 X2 X1 X0
117 JOY1DAT Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 X7 X6 X5 X4 X3 X2 X1 X0
120 0=LEFT CONTROLLER PAIR, 1=RIGHT CONTROLLER PAIR.
129 | 0 | M0H | JOY0DAT Horizontal Clock |
146 Bits 1 and 0 of each counter (Y1-Y0,X1-X0) may be
176 JOYxDAT Y7 Y6 Y5 Y4 Y3 Y2 xx xx X7 X6 X5 X4 X3 X2 xx xx
177 JOYxDAT Y7 Y6 Y5 Y4 Y3 Y2 xx xx X7 X6 X5 X4 X3 X2 xx xx
197 RIGHT Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 X7 X6 X5 X4 X3 X2 X1 X0
198 LEFT Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 X7 X6 X5 X4 X3 X2 X1 X0
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| /Documentation/devicetree/bindings/mtd/ |
| D | ti,am654-hbmc.yaml | 31 "^flash@[0-1],[0-9a-f]+$":
54 reg = <0x0 0x47034000 0x0 0x100>,
55 <0x5 0x00000000 0x1 0x0000000>;
56 ranges = <0x0 0x0 0x5 0x00000000 0x4000000>, /* CS0 - 64MB */
57 <0x1 0x0 0x5 0x04000000 0x4000000>; /* CS1 - 64MB */
58 clocks = <&k3_clks 102 0>;
62 mux-controls = <&hbmc_mux 0>;
64 flash@0,0 {
66 reg = <0x0 0x0 0x4000000>;
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| /Documentation/devicetree/bindings/sound/ |
| D | adi,adau1701.txt | 31 reg = <0x34>;
32 reset-gpio = <&gpio 23 0>;
35 adi,pll-mode-gpios = <&gpio 24 0 &gpio 25 0>;
36 adi,pin-config = /bits/ 8 <0x4 0x7 0x5 0x5 0x4 0x4
37 0x4 0x4 0x4 0x4 0x4 0x4>;
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| D | qcom,pm8916-wcd-analog-codec.yaml | 110 reg = <0x1 SPMI_USID>;
112 #size-cells = <0>;
116 reg = <0xf000>;
120 interrupts = <0x1 0xf0 0x0 IRQ_TYPE_NONE>,
121 <0x1 0xf0 0x1 IRQ_TYPE_NONE>,
122 <0x1 0xf0 0x2 IRQ_TYPE_NONE>,
123 <0x1 0xf0 0x3 IRQ_TYPE_NONE>,
124 <0x1 0xf0 0x4 IRQ_TYPE_NONE>,
125 <0x1 0xf0 0x5 IRQ_TYPE_NONE>,
126 <0x1 0xf0 0x6 IRQ_TYPE_NONE>,
[all …]
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| /Documentation/devicetree/bindings/powerpc/fsl/ |
| D | mpic-msgr.txt | 38 Numbers shall start at 0.
49 reg = <0x41400 0x200>;
50 // Message registers 0 and 2 in this block can receive interrupts on
51 // sources 0xb0 and 0xb2, respectively.
52 interrupts = <0xb0 2 0xb2 2>;
53 mpic-msgr-receive-mask = <0x5>;
58 reg = <0x42400 0x200>;
59 // Message registers 0 and 2 in this block can receive interrupts on
60 // sources 0xb4 and 0xb6, respectively.
61 interrupts = <0xb4 2 0xb6 2>;
[all …]
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| /Documentation/devicetree/bindings/goldfish/ |
| D | events.txt | 15 reg = <0x9040000 0x1000>;
16 interrupts = <0x5>;
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| /Documentation/devicetree/bindings/pci/ |
| D | xlnx,xdma-host.yaml | 50 - const: 0
51 - const: 0
52 - const: 0
68 const: 0
124 reg = <0x0 0xa0000000 0x0 0x10000000>;
125 ranges = <0x2000000 0x0 0xb0000000 0x0 0xb0000000 0x0 0x1000000>,
126 <0x43000000 0x5 0x0 0x5 0x0 0x0 0x1000000>;
135 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
136 interrupt-map = <0 0 0 1 &pcie_intc_0 0>,
137 <0 0 0 2 &pcie_intc_0 1>,
[all …]
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| D | mvebu-pci.txt | 23 0x82000000 0 r MBUS_ID(0xf0, 0x01) r 0 s
32 registers area. This range entry translates the '0x82000000 0 r' PCI
33 address into the 'MBUS_ID(0xf0, 0x01) r' CPU address, which is part
34 of the internal register window (as identified by MBUS_ID(0xf0,
35 0x01)).
39 0x8t000000 s 0 MBUS_ID(w, a) 0 1 0
79 value is 0.
99 bus-range = <0x00 0xff>;
103 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
104 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
[all …]
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| /Documentation/devicetree/bindings/leds/ |
| D | leds-lp50xx.yaml | 38 lp5009/12 - 0x14, 0x15, 0x16, 0x17
39 lp5018/24 - 0x28, 0x29, 0x2a, 0x2b
40 lp5030/36 - 0x30, 0x31, 0x32, 0x33
53 const: 0
56 '^multi-led@[0-9a-f]$':
74 const: 0
77 "^led@[0-9a-f]+$":
102 #size-cells = <0>;
106 reg = <0x14>;
108 #size-cells = <0>;
[all …]
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| /Documentation/ABI/testing/ |
| D | sysfs-class-extcon | 46 HDMI=0
48 EAR_JACK=0
55 state number starting with 0x::
57 # echo 0xHEX > state
73 "X" (integer between 0 and 31) of an extcon device.
80 state of cable "X" (integer between 0 and 31) of an extcon
81 device. The state value is either 0 (detached) or 1
90 {0x3, 0x5, 0xC, 0x0}, then the output is::
93 0x3
94 0x5
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| D | sysfs-driver-qat_rl | 47 bit 1 == ring pair id 0; bit 3 == ring pair id 2.
66 0x5
69 # echo 0x5 > /sys/bus/pci/devices/<BDF>/qat_rl/rp
102 0x5 ## ring pair ID 0 and ring pair ID 2
224 0
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| /Documentation/devicetree/bindings/net/ |
| D | apm-xgene-mdio.txt | 8 - #size-cells: Must be <0>.
21 #size-cells = <0>;
22 reg = <0x0 0x17020000 0x0 0xd100>;
23 clocks = <&menetclk 0>;
29 reg = <0x3>;
32 reg = <0x4>;
35 reg = <0x5>;
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| D | nxp,tja11xx.yaml | 66 "^ethernet-phy@[0-9a-f]+$":
75 minimum: 0
89 #size-cells = <0>;
93 reg = <0x4>;
100 #size-cells = <0>;
103 reg = <0x4>;
105 #size-cells = <0>;
108 reg = <0x5>;
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| /Documentation/devicetree/bindings/mailbox/ |
| D | xgene-slimpro-mailbox.txt | 14 - interrupts: 8 interrupts must be from 0 to 7, interrupt 0 define the
15 the interrupt for mailbox channel 0 and interrupt 1 for
25 reg = <0x0 0x10540000 0x0 0xa000>;
27 interrupts = <0x0 0x0 0x4>,
28 <0x0 0x1 0x4>,
29 <0x0 0x2 0x4>,
30 <0x0 0x3 0x4>,
31 <0x0 0x4 0x4>,
32 <0x0 0x5 0x4>,
33 <0x0 0x6 0x4>,
[all …]
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| /Documentation/devicetree/bindings/phy/ |
| D | hisilicon,hi3670-usb3.yaml | 20 const: 0
58 #phy-cells = <0>;
62 hisilicon,eye-diagram-param = <0xfdfee4>;
63 hisilicon,tx-vboost-lvl = <0x5>;
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| /Documentation/devicetree/bindings/bus/ |
| D | st,stm32-etzpc.yaml | 47 "^.*@[0-9a-f]+$":
78 reg = <0x5c007000 0x400>;
86 reg = <0x4c001000 0x400>;
91 dmas = <&dmamux1 43 0x400 0x5>,
92 <&dmamux1 44 0x400 0x1>;
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| /Documentation/PCI/endpoint/function/binding/ |
| D | pci-ntb.rst | 12 vendorid should be 0x104c
13 deviceid should be 0xb00d for TI's J721E SoC
16 subclass_code should be 0x00
17 baseclass_code should be 0x5
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| /Documentation/i2c/busses/ |
| D | i2c-mlxcpld.rst | 28 CPBLTY 0x0 - capability reg.
32 CTRL 0x1 - control reg.
34 HALF_CYC 0x4 - cycle reg.
37 I2C_HOLD 0x5 - hold reg.
40 CMD 0x6 - command reg.
41 Bit 0, 0 = write, 1 = read.
44 NUM_DATA 0x7 - data size reg.
46 NUM_ADDR 0x8 - address reg.
48 STATUS 0x9 - status reg.
49 Bit 0 - transaction is completed.
[all …]
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| /Documentation/devicetree/bindings/pinctrl/ |
| D | fsl,imx6ul-pinctrl.yaml | 61 PAD_CTL_PUS_100K_DOWN (0 << 14)
68 PAD_CTL_SPEED_LOW (0 << 6)
71 PAD_CTL_DSE_DISABLE (0 << 3)
79 PAD_CTL_SRE_FAST (1 << 0)
80 PAD_CTL_SRE_SLOW (0 << 0)
97 reg = <0x020e0000 0x4000>;
101 0x0084 0x0310 0x0000 0 0 0x1b0b1
102 0x0088 0x0314 0x0624 0 3 0x1b0b1
109 reg = <0x02290000 0x4000>;
113 0x0010 0x0054 0x0000 0x5 0x0 0x130b0
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| /Documentation/devicetree/bindings/mmc/ |
| D | sdhci-am654.yaml | 64 minimum: 0
65 maximum: 0xf
70 minimum: 0
71 maximum: 0xf
76 minimum: 0
77 maximum: 0xf
82 minimum: 0
83 maximum: 0xf
88 minimum: 0
89 maximum: 0xf
[all …]
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | marvell,icu.txt | 44 have a different number within [0:206].
50 reg = <0x1e0000 0x440>;
54 reg = <0x10 0x20>;
62 reg = <0x50 0x10>;
90 ICU_GRP_NSR (0x0) : Shared peripheral interrupt, non-secure
91 ICU_GRP_SR (0x1) : Shared peripheral interrupt, secure
92 ICU_GRP_SEI (0x4) : System error interrupt
93 ICU_GRP_REI (0x5) : RAM error interrupt
102 reg = <0x1e0000 0x440>;
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| /Documentation/networking/ |
| D | net_failover.rst | 54 <address type='pci' domain='0x0000' bus='0x42' slot='0x02' function='0x5'/>
106 + if [ -d "/sys/class/net/${INTERFACE}/master" ]; then exit 0; fi
131 <address type='pci' domain='0x0000' bus='0x42' slot='0x02' function='0x5'/>
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| /Documentation/devicetree/bindings/net/dsa/ |
| D | lantiq,gswip.yaml | 50 const: 0
65 "^gphy@[0-9a-f]{1,2}$":
72 minimum: 0
104 reg = <0xe108000 0x3100>, /* switch */
105 <0xe10b100 0xd8>, /* mdio */
106 <0xe10b1d8 0x130>; /* mii */
107 dsa,member = <0 0>;
111 #size-cells = <0>;
113 port@0 {
114 reg = <0>;
[all …]
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