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/Documentation/devicetree/bindings/pci/
Dfaraday,ftpci100.yaml18 The host controller appear on the PCI bus with vendor ID 0x159b (Faraday
19 Technology) and product ID 0x4321.
34 interrupt-map-mask = <0xf800 0 0 7>;
36 <0x4800 0 0 1 &pci_intc 0>, /* Slot 9 */
37 <0x4800 0 0 2 &pci_intc 1>,
38 <0x4800 0 0 3 &pci_intc 2>,
39 <0x4800 0 0 4 &pci_intc 3>,
40 <0x5000 0 0 1 &pci_intc 1>, /* Slot 10 */
41 <0x5000 0 0 2 &pci_intc 2>,
42 <0x5000 0 0 3 &pci_intc 3>,
[all …]
Dv3-v360epc-pci.txt18 each be exactly 256MB (0x10000000) in size.
38 reg = <0x62000000 0x10000>, <0x61000000 0x01000000>;
42 bus-range = <0x00 0xff>;
43 ranges = 0x01000000 0 0x00000000 /* I/O space @00000000 */
44 0x60000000 0 0x01000000 /* 16 MiB @ LB 60000000 */
45 0x02000000 0 0x40000000 /* non-prefectable memory @40000000 */
46 0x40000000 0 0x10000000 /* 256 MiB @ LB 40000000 1:1 */
47 0x42000000 0 0x50000000 /* prefetchable memory @50000000 */
48 0x50000000 0 0x10000000>; /* 256 MiB @ LB 50000000 1:1 */
49 dma-ranges = <0x02000000 0 0x20000000 /* EBI memory space */
[all …]
Dmvebu-pci.txt23 0x82000000 0 r MBUS_ID(0xf0, 0x01) r 0 s
32 registers area. This range entry translates the '0x82000000 0 r' PCI
33 address into the 'MBUS_ID(0xf0, 0x01) r' CPU address, which is part
34 of the internal register window (as identified by MBUS_ID(0xf0,
35 0x01)).
39 0x8t000000 s 0 MBUS_ID(w, a) 0 1 0
79 value is 0.
99 bus-range = <0x00 0xff>;
103 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
104 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
[all …]
/Documentation/devicetree/bindings/tpm/
Dtcg,tpm-tis-mmio.yaml31 at least 0x5000 bytes
46 reg = <0x90000 0x5000>;
/Documentation/devicetree/bindings/powerpc/fsl/
Dpamu.txt12 "fsl,pamu-v1.0". The second is "fsl,pamu".
18 PAMU v1.0, on an SOC that has five PAMU devices, the size
19 is 0x5000.
56 For PAMU v1.0, this size is 0x1000.
95 compatible = "fsl,pamu-v1.0", "fsl,pamu";
96 reg = <0x20000 0x5000>;
97 ranges = <0 0x20000 0x5000>;
98 fsl,portid-mapping = <0xf80000>;
102 24 2 0 0
105 pamu0: pamu@0 {
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Dinterlaken-lac.txt31 There is a full register set at 0x0000-0x0FFF (also known as the "hypervisor"
32 version), and a subset at 0x1000-0x1FFF. The former is a superset of the
45 IP Block Revision Register (IPBRR0) at offset 0x0BF8.
51 0x02000100 T4240
78 reg = <0x229000 0x1000>;
84 reg = <0x228000 0x1000>;
136 Register (IPBRR0), at offset 0x0BF8, and Y is the Minor version
161 #address-cells = <0x1>;
162 #size-cells = <0x1>;
164 ranges = <0x0 0xf 0xf4400000 0x20000>;
[all …]
/Documentation/devicetree/bindings/ata/
Dmarvell.txt11 - phy-names : Should be "0", "1", etc, one number per phandle
17 reg = <0x80000 0x5000>;
20 phy-names = "0", "1";
/Documentation/devicetree/bindings/memory-controllers/
Dmediatek,mt7621-memc.yaml31 reg = <0x5000 0x1000>;
/Documentation/devicetree/bindings/arm/
Darm,cci-400.yaml24 pattern: "^cci(@[0-9a-f]+)?$"
43 "^slave-if@[0-9a-f]+$":
65 "^pmu@[0-9a-f]+$":
119 arm,hbi = <0x249>;
129 * registers sits at address 0x000000002c090000.
131 * CCI slave interface @0x000000002c091000 is connected to dma
134 * CCI slave interface @0x000000002c094000 is connected to CPUs
137 * CCI slave interface @0x000000002c095000 is connected to CPUs
142 #size-cells = <0>;
145 CPU0: cpu@0 {
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/Documentation/devicetree/bindings/pmem/
Dpmem-region.txt48 * 0x5000 to 0x5fff that is backed by non-volatile memory.
52 reg = <0x00005000 0x00001000>;
61 reg = < 0x00006000 0x00001000
62 0x00008000 0x00001000 >;
/Documentation/devicetree/bindings/mtd/partitions/
Dnvmem-cells.yaml45 reg = <0x1200000 0x0140000>;
51 macaddr_gmac1: macaddr_gmac1@0 {
52 reg = <0x0 0x6>;
56 reg = <0x6 0x6>;
60 reg = <0x1000 0x2f20>;
64 reg = <0x5000 0x2f20>;
73 partition@0 {
75 reg = <0x000000 0x100000>;
82 reg = <0x100000 0xe00000>;
88 reg = <0xf00000 0x100000>;
[all …]
/Documentation/devicetree/bindings/media/
Dmediatek,mdp3-wrot.yaml81 reg = <0x14005000 0x1000>;
82 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
/Documentation/devicetree/bindings/display/mediatek/
Dmediatek,aal.yaml87 reg = <0 0x14015000 0 0x1000>;
91 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
Dmediatek,ethdr.yaml55 - description: video frontend 0 clock
57 - description: graphic frontend 0 clock
61 - description: video frontend 0 async clock
63 - description: graphic frontend 0 async clock
89 - description: video frontend 0 async reset
91 - description: graphic frontend 0 async reset
140 reg = <0 0x1c114000 0 0x1000>,
141 <0 0x1c115000 0 0x1000>,
142 <0 0x1c117000 0 0x1000>,
143 <0 0x1c119000 0 0x1000>,
[all …]
/Documentation/devicetree/bindings/remoteproc/
Dqcom,sc7280-adsp-pil.yaml153 reg = <0x03000000 0x5000>,
154 <0x0355b000 0x10>;
157 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
176 qcom,halt-regs = <&tcsr_mutex 0x23000 0x25000 0x28000 0x33000>;
180 qcom,smem-states = <&adsp_smp2p_out 0>;
Dqcom,msm8996-mss-pil.yaml345 reg = <0x04080000 0x408>, <0x04180000 0x48>;
349 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
379 qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>;
383 qcom,smem-states = <&modem_smp2p_out 0>;
/Documentation/devicetree/bindings/soc/samsung/
Dexynos-pmu.yaml85 pattern: '^clkout([0-9]|[12][0-9]|3[0-1])$'
193 reg = <0x10040000 0x5000>;
203 #phy-cells = <0>;
/Documentation/devicetree/bindings/mmc/
Darm,pl18x.yaml92 description: the MMIO memory window must be exactly 4KB (0x1000) and the
112 DAT[0].
142 pins CMD, DAT[0], DAT[1], DAT[2] and DAT[3].
189 reg = <0x5000 0x1000>;
200 reg = <0x80126000 0x1000>;
201 interrupts = <0 60 IRQ_TYPE_LEVEL_HIGH>;
202 dmas = <&dma 29 0 0x2>, <&dma 29 0 0x0>;
210 cd-gpios = <&gpio2 31 0x4>;
222 reg = <0x101f6000 0x1000>;
242 arm,primecell-periphid = <0x10153180>;
[all …]
/Documentation/hwmon/
Dcoretemp.rst9 CPUID: family 0x6, models
11 - 0xe (Pentium M DC), 0xf (Core 2 DC 65nm),
12 - 0x16 (Core 2 SC 65nm), 0x17 (Penryn 45nm),
13 - 0x1a (Nehalem), 0x1c (Atom), 0x1e (Lynnfield),
14 - 0x26 (Tunnel Creek Atom), 0x27 (Medfield Atom),
15 - 0x36 (Cedar Trail Atom)
37 1 degree C. Valid temperatures are from 0 to TjMax degrees C, because
182 X5000 90-95
/Documentation/trace/coresight/
Dcoresight-etm4x-reference.rst35 ``$> echo 0x012 > mode``
52 - > 0 : Programs up the hardware with the current values held in the driver
55 - = 0 : disable trace hardware.
70 ``$> 0``
117 - 0 for include
120 ``$> echo 0x0000 0x2000 0 > addr_range``
203 ``$> echo 0x4F > addr_exlevel_s_ns``
208 :Trace Registers: ACATR[idx,{1:0}]
229 ``addr_cmp[0] range 0x0 0xffffffffffffffff include ctrl(0x4b00)``
273 ``0x1``
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