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/Documentation/admin-guide/
Dbtmrvl.rst14 bit 8:0 -- Gap
18 It could be any valid GPIO pin# (e.g. 0-7) or 0xff (SDIO interface
22 wakeup event, or 0xff for special host sleep setting.
26 # Use SDIO interface to wake up the host and set GAP to 0x80:
27 echo 0xff80 > /debug/btmrvl/config/gpiogap
30 # Use GPIO pin #3 to wake up the host and set GAP to 0xff:
31 echo 0x03ff > /debug/btmrvl/config/gpiogap
40 0 -- Disable auto sleep mode
49 echo 0 > /debug/btmrvl/config/psmode
59 0 -- Wake up firmware
[all …]
/Documentation/devicetree/bindings/power/supply/
Dcw2015_battery.yaml61 #size-cells = <0>;
65 reg = <0x62>;
67 0x17 0x67 0x80 0x73 0x6E 0x6C 0x6B 0x63
68 0x77 0x51 0x5C 0x58 0x50 0x4C 0x48 0x36
69 0x15 0x0C 0x0C 0x19 0x5B 0x7D 0x6F 0x69
70 0x69 0x5B 0x0C 0x29 0x20 0x40 0x52 0x59
71 0x57 0x56 0x54 0x4F 0x3B 0x1F 0x7F 0x17
72 0x06 0x1A 0x30 0x5A 0x85 0x93 0x96 0x2D
73 0x48 0x77 0x9C 0xB3 0x80 0x52 0x94 0xCB
74 0x2F 0x00 0x64 0xA5 0xB5 0x11 0xF0 0x11
Drichtek,rt9467.yaml65 #size-cells = <0>;
69 reg = <0x5b>;
/Documentation/devicetree/bindings/iio/chemical/
Dams,ccs811.yaml43 #size-cells = <0>;
47 reg = <0x5b>;
/Documentation/devicetree/bindings/ptp/
Dptp-idtcm.yaml64 #size-cells = <0>;
67 reg = <0x5b>;
/Documentation/devicetree/bindings/mfd/
Dact8945a.txt14 reg = <0x5b>;
72 pinctrl-0 = <&pinctrl_charger_chglev &pinctrl_charger_lbo &pinctrl_charger_irq>;
/Documentation/devicetree/bindings/regulator/
Dactive-semi,act8865.yaml95 #size-cells = <0>;
99 reg = <0x5b>;
Dmicrochip,mcp16502.yaml81 #size-cells = <0>;
85 reg = <0x5b>;
Dactive-semi,act8945a.yaml133 #size-cells = <0>;
137 reg = <0x5b>;
247 pinctrl-0 = <&pinctrl_charger_chglev &pinctrl_charger_lbo &pinctrl_charger_irq>;
/Documentation/hwmon/
Dw83781d.rst10 Addresses scanned: I2C 0x28 - 0x2f, ISA 0x290 (8 I/O ports)
18 Addresses scanned: I2C 0x28 - 0x2f, ISA 0x290 (8 I/O ports)
26 Addresses scanned: I2C 0x2d
34 Addresses scanned: I2C 0x28 - 0x2f
52 Use 'init=0' to bypass initializing the chip.
56 (default 0)
62 a certain chip. Typical usage is `force_subclients=0,0x2d,0x4a,0x4b`
63 to force the subclients of chip 0x2d on bus 0 to i2c addresses
64 0x4a and 0x4b. This parameter is useful for certain Tyan boards.
80 | as99127f | 7 | 3 | 0 | 3 | 0x31 | 0x12c3 | yes | no |
[all …]
/Documentation/scsi/
DChangeLog.megaraid_sas50 6. Add support for MegaRAID Fury (device ID-0x005f) 12Gb/s controllers.
156 4. Call tasklet_schedule() even if outbound_intr_status == 0 for MFI based
190 6. Add code to support MegaRAID 9265/9285 controllers device id (0x5b).
246 1. Add the pad_0 in mfi frame structure to 0 to fix the
533 iv. Default value of megasas_dbg_lvl set to 0
573 New device id 0x413 added.
599 i. Support for 1078 type (ppc IOP) controller, device id : 0x60 added.