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/Documentation/devicetree/bindings/pci/
Dfaraday,ftpci100.yaml18 The host controller appear on the PCI bus with vendor ID 0x159b (Faraday
19 Technology) and product ID 0x4321.
34 interrupt-map-mask = <0xf800 0 0 7>;
36 <0x4800 0 0 1 &pci_intc 0>, /* Slot 9 */
37 <0x4800 0 0 2 &pci_intc 1>,
38 <0x4800 0 0 3 &pci_intc 2>,
39 <0x4800 0 0 4 &pci_intc 3>,
40 <0x5000 0 0 1 &pci_intc 1>, /* Slot 10 */
41 <0x5000 0 0 2 &pci_intc 2>,
42 <0x5000 0 0 3 &pci_intc 3>,
[all …]
Dv3-v360epc-pci.txt18 each be exactly 256MB (0x10000000) in size.
38 reg = <0x62000000 0x10000>, <0x61000000 0x01000000>;
42 bus-range = <0x00 0xff>;
43 ranges = 0x01000000 0 0x00000000 /* I/O space @00000000 */
44 0x60000000 0 0x01000000 /* 16 MiB @ LB 60000000 */
45 0x02000000 0 0x40000000 /* non-prefectable memory @40000000 */
46 0x40000000 0 0x10000000 /* 256 MiB @ LB 40000000 1:1 */
47 0x42000000 0 0x50000000 /* prefetchable memory @50000000 */
48 0x50000000 0 0x10000000>; /* 256 MiB @ LB 50000000 1:1 */
49 dma-ranges = <0x02000000 0 0x20000000 /* EBI memory space */
[all …]
/Documentation/devicetree/bindings/net/
Dnixge.txt27 reg = <0x40000000 0x4000
28 0x41002000 0x2000>;
34 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>, <0 30 IRQ_TYPE_LEVEL_HIGH>;
52 reg = <0x40000000 0x6000>;
57 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>, <0 30 IRQ_TYPE_LEVEL_HIGH>;
68 reg = <0x40000000 0x6000>;
73 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>, <0 30 IRQ_TYPE_LEVEL_HIGH>;
/Documentation/devicetree/bindings/watchdog/
Dmstar,msc313e-wdt.yaml10 - Daniel Palmer <daniel@0x0f.com>
38 reg = <0x6000 0x1f>;
/Documentation/devicetree/bindings/display/
Dbrcm,bcm2835-hvs.yaml49 reg = <0x7e400000 0x6000>;
Damlogic,meson-g12a-dw-mipi-dsi.yaml59 port@0:
68 - port@0
88 reg = <0x6000 0x400>;
98 #size-cells = <0>;
101 mipi_dsi_venc_port: port@0 {
102 reg = <0>;
Dxylon,logicvc-display.yaml69 # Parallel RGB interface (C_DISPLAY_INTERFACE == 0)
83 # RGB colorspace (C_DISPLAY_COLOR_SPACE == 0)
123 const: 0
126 "^layer@[0-9]+$":
139 # RGB colorspace (C_LAYER_X_TYPE == 0)
141 # YUV packed colorspace (C_LAYER_X_TYPE == 0)
147 # Alpha is configured layer-wide (C_LAYER_X_ALPHA_MODE == 0)
182 - layer@0
216 reg = <0x43c00000 0x6000>;
221 logicvc_display: display@0 {
[all …]
/Documentation/devicetree/bindings/mfd/
Dxylon,logicvc.yaml46 "^gpio@[0-9a-f]+$":
49 "^display@[0-9a-f]+$":
62 reg = <0x43c00000 0x6000>;
/Documentation/devicetree/bindings/gpio/
Dxylon,logicvc-gpio.yaml20 - GPIO[4:0] (display control) mapped to index 0-4
28 pattern: "^gpio@[0-9a-f]+$"
58 reg = <0x43c00000 0x6000>;
65 reg = <0x40 0x40>;
/Documentation/devicetree/bindings/rtc/
Dqcom-pm8xxx-rtc.yaml69 #size-cells = <0>;
71 pmic@0 {
73 reg = <0x0 SPMI_USID>;
75 #size-cells = <0>;
79 reg = <0x6000>, <0x6100>;
81 interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>;
/Documentation/devicetree/bindings/soc/mediatek/
Dmediatek,wdma.yaml74 reg = <0x14006000 0x1000>;
75 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>;
/Documentation/devicetree/bindings/interconnect/
Dqcom,msm8996.yaml111 reg = <0x00408000 0x5a000>;
117 reg = <0x00543000 0x6000>;
/Documentation/devicetree/bindings/phy/
Dphy-mvebu-comphy.txt21 * Lane 0 (USB3/GbE)
26 - #size-cells: should be 0.
47 reg = <0x120000 0x6000>;
53 #size-cells = <0>;
55 CP11X_LABEL(comphy0): phy@0 {
56 reg = <0>;
68 reg = <0x18300 0x300>,
69 <0x1F000 0x400>,
70 <0x5C000 0x400>,
71 <0xe0178 0x8>;
[all …]
/Documentation/devicetree/bindings/display/mediatek/
Dmediatek,gamma.yaml90 reg = <0 0x14016000 0 0x1000>;
94 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x6000 0x1000>;
/Documentation/devicetree/bindings/crypto/
Dqcom-qce.yaml160 reg = <0xfd45a000 0x6000>;
167 iommus = <&apps_smmu 0x584 0x0011>,
168 <&apps_smmu 0x586 0x0011>,
169 <&apps_smmu 0x594 0x0011>,
170 <&apps_smmu 0x596 0x0011>;
Dfsl,sec-v4.0.yaml5 $id: http://devicetree.org/schemas/crypto/fsl,sec-v4.0.yaml#
42 - const: fsl,sec-v5.0
43 - const: fsl,sec-v4.0
47 - fsl,sec-v5.0
48 - const: fsl,sec-v4.0
49 - const: fsl,sec-v4.0
83 '^jr@[0-9a-f]+$':
98 - const: fsl,sec-v5.0-job-ring
99 - const: fsl,sec-v4.0-job-ring
101 - const: fsl,sec-v5.0-job-ring
[all …]
/Documentation/devicetree/bindings/soc/qcom/
Dqcom,geni-se.yaml67 "spi@[0-9a-f]+$":
75 "i2c@[0-9a-f]+$":
80 "serial@[0-9a-f]+$":
104 "spi@[0-9a-f]+$": false
105 "serial@[0-9a-f]+$": false
131 reg = <0 0x008c0000 0 0x6000>;
141 reg = <0 0xa94000 0 0x4000>;
146 pinctrl-0 = <&qup_1_i2c_5_active>;
149 #size-cells = <0>;
154 reg = <0 0xa88000 0 0x7000>;
[all …]
/Documentation/devicetree/bindings/net/can/
Dxilinx,can.yaml125 reg = <0xe0008000 0x1000>;
130 tx-fifo-depth = <0x40>;
131 rx-fifo-depth = <0x40>;
137 reg = <0x40000000 0x10000>;
138 clocks = <&clkc 0>, <&clkc 1>;
142 tx-fifo-depth = <0x40>;
143 rx-fifo-depth = <0x40>;
150 reg = <0x40000000 0x2000>;
151 clocks = <&clkc 0>, <&clkc 1>;
155 tx-mailbox-count = <0x20>;
[all …]
/Documentation/devicetree/bindings/mips/brcm/
Dsoc.txt38 reg = <0x410000 0x400>;
57 space, must be 0 here, and the register start and length of
65 memory-controller@0 {
67 ranges = <0x0 0x0 0xa000>;
101 reg = <0x6000 0xc8>;
121 reg = <0x2000 0x300>;
133 "brcm,brcmstb-memc-arb-v10.0.0.0"
141 compatible = "brcm,brcmstb-memc-arb-v10.0.0.0";
142 reg = <0x1000 0x248>;
164 reg = <0x4067c0 0x40>;
/Documentation/hwmon/
Dvia686a.rst26 force_addr=0xaddr Set the I/O base address. Useful for boards that
32 Example: 'modprobe via686a force_addr=0x6000'
/Documentation/devicetree/bindings/pinctrl/
Dpinctrl-st.txt55 - 0 = active high
86 reg = <0x0961f080 0x4>;
90 ranges = <0 0x09610000 0x6000>;
97 reg = <0x0 0x100>;
151 as non inverted clock retimed with CLK_B and delay of 0 pico seconds:
158 mmcclk = <&PIO13 4 ALT4 BIDIR_PU NICLK 0 CLK_B>;
173 pinctrl-0 = <&pinctrl_mmc>;
/Documentation/devicetree/bindings/remoteproc/
Dti,pru-rproc.yaml19 The K3 SoCs containing ICSSG v1.0 (eg: AM65x SR1.0) also have two Auxiliary
21 containing the revised ICSSG v1.1 (eg: J721E, AM65x SR2.0) have an extra two
46 - ti,am654-tx-pru # for Tx_PRUs in K3 AM65x SR2.0 SoCs
90 pattern: "^rtu@[0-9a-f]+$"
102 pattern: "^txpru@[0-9a-f]+"
106 pattern: "^pru@[0-9a-f]+$"
119 pruss_tm: target-module@300000 { /* 0x4a300000, ap 9 04.0 */
123 ranges = <0x0 0x300000 0x80000>;
125 pruss: pruss@0 {
127 reg = <0x0 0x80000>;
[all …]
/Documentation/devicetree/bindings/powerpc/fsl/
Dinterlaken-lac.txt31 There is a full register set at 0x0000-0x0FFF (also known as the "hypervisor"
32 version), and a subset at 0x1000-0x1FFF. The former is a superset of the
45 IP Block Revision Register (IPBRR0) at offset 0x0BF8.
51 0x02000100 T4240
78 reg = <0x229000 0x1000>;
84 reg = <0x228000 0x1000>;
136 Register (IPBRR0), at offset 0x0BF8, and Y is the Minor version
161 #address-cells = <0x1>;
162 #size-cells = <0x1>;
164 ranges = <0x0 0xf 0xf4400000 0x20000>;
[all …]
/Documentation/filesystems/ext4/
Dinodes.rst24 is no inode 0.
40 * - 0x0
44 * - 0x2
48 * - 0x4
52 * - 0x8
58 * - 0xC
65 * - 0x10
72 * - 0x14
76 * - 0x18
80 * - 0x1A
[all …]
/Documentation/admin-guide/laptops/
Dthinkpad-acpi.rst153 (output in hex format: 0xAAAABBCC), where:
211 events. If a key is "masked" (bit set to 0 in the mask), the firmware
240 echo 0xffffffff > /proc/acpi/ibm/hotkey -- enable all hot keys
241 echo 0 > /proc/acpi/ibm/hotkey -- disable all possible hot keys
262 Returns 0.
269 to this value. This is always 0x80c, because those are
276 0: returns -EPERM
323 0 and 25 Hz. Polling is only carried out when strictly
337 attribute will read 0 if the switch is in the "radios
345 will read 0 if the ThinkPad is in normal mode, and
[all …]

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