Searched +full:0 +full:x7 (Results 1 – 25 of 80) sorted by relevance
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| /Documentation/devicetree/bindings/gpio/ |
| D | gpio-stp-xway.yaml | 20 pattern: "^gpio@[0-9a-f]+$"
41 minimum: 0x000000
42 maximum: 0xffffff
49 minimum: 0x0
50 maximum: 0x7
57 minimum: 0x0
58 maximum: 0x3
71 minimum: 0x0
72 maximum: 0x7
86 reg = <0xE100BB0 0x40>;
[all …]
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| /Documentation/input/devices/ |
| D | alps.rst | 32 E8-E6-E6-E6-E9. An ALPS touchpad should respond with either 00-00-0A or
33 00-00-64 if no buttons are pressed. The bits 0-2 of the first byte will be 1s
45 The new ALPS touchpads have an E7 signature of 73-03-50 or 73-03-0A but
94 byte 0: 0 0 YSGN XSGN 1 M R L
95 byte 1: X7 X6 X5 X4 X3 X2 X1 X0
109 byte 0: 1 0 0 0 1 x9 x8 x7
110 byte 1: 0 x6 x5 x4 x3 x2 x1 x0
111 byte 2: 0 ? ? l r ? fin ges
112 byte 3: 0 ? ? ? ? y9 y8 y7
113 byte 4: 0 y6 y5 y4 y3 y2 y1 y0
[all …]
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| D | elantech.rst | 69 (TouchPadOff=0) will also disable the buttons associated with the touchpad.
99 By echoing "0" to this file all debugging will be turned OFF.
113 By echoing "0" to this file parity checking will be turned OFF. Any
128 Sets crc_enabled to 0/1. The name "crc_enabled" is the official name of
138 "0" or "1" to this file will set the state to "0" or "1".
143 To detect the hardware version, read the version number as param[0].param[1].param[2]::
164 Probably all the versions with param[0] <= 01 can be considered as
179 echo -n 0x16 > reg_10
183 bit 7 6 5 4 3 2 1 0
197 bit 7 6 5 4 3 2 1 0
[all …]
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| /Documentation/ABI/testing/ |
| D | sysfs-bus-event_source-devices-hv_24x7 | 14 domain = "config:0-3"
15 lpar = "config:0-15"
21 PM_PB_CYC = "domain=1,offset=0x80,chip=?,lpar=0x0"
30 Provides access to the binary "24x7 catalog" provided by the
34 https://raw.githubusercontent.com/jmesmon/catalog-24x7/master/hv-24x7-catalog.h
47 Exposes the "version" field of the 24x7 catalog. This is also
76 HCALLs to retrieve hv-24x7 pmu event counter data.
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | fsl,ls-extirq.yaml | 38 const: 0
76 - const: 0x7
77 - const: 0
92 - const: 0xf
93 - const: 0
115 - const: 0xf
116 - const: 0
126 #address-cells = <0>;
128 reg = <0x1ac 4>;
130 <0 0 &gic GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
[all …]
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| /Documentation/filesystems/ext4/ |
| D | directory.rst | 27 directory entries are signified by inode = 0. By default the filesystem
44 * - 0x0
48 * - 0x4
52 * - 0x6
56 * - 0x8
76 * - 0x0
80 * - 0x4
84 * - 0x6
88 * - 0x7
92 * - 0x8
[all …]
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| /Documentation/devicetree/bindings/mailbox/ |
| D | xgene-slimpro-mailbox.txt | 14 - interrupts: 8 interrupts must be from 0 to 7, interrupt 0 define the
15 the interrupt for mailbox channel 0 and interrupt 1 for
25 reg = <0x0 0x10540000 0x0 0xa000>;
27 interrupts = <0x0 0x0 0x4>,
28 <0x0 0x1 0x4>,
29 <0x0 0x2 0x4>,
30 <0x0 0x3 0x4>,
31 <0x0 0x4 0x4>,
32 <0x0 0x5 0x4>,
33 <0x0 0x6 0x4>,
[all …]
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| /Documentation/devicetree/bindings/cpufreq/ |
| D | imx-cpufreq-dt.txt | 15 0: Consumer
27 /* grade >= 0, consumer only */
28 opp-supported-hw = <0xf>, <0x3>;
35 opp-supported-hw = <0xe>, <0x7>;
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| /Documentation/devicetree/bindings/sound/ |
| D | adi,adau1701.txt | 31 reg = <0x34>;
32 reset-gpio = <&gpio 23 0>;
35 adi,pll-mode-gpios = <&gpio 24 0 &gpio 25 0>;
36 adi,pin-config = /bits/ 8 <0x4 0x7 0x5 0x5 0x4 0x4
37 0x4 0x4 0x4 0x4 0x4 0x4>;
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| /Documentation/devicetree/bindings/firmware/ |
| D | qemu,fw-cfg-mmio.yaml | 34 * Bytes 0x0 to 0x7 cover the data register.
35 * Bytes 0x8 to 0x9 cover the selector register.
52 reg = <0x9020000 0xa>;
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| /Documentation/admin-guide/ |
| D | lcd-panel-cgram.rst | 6 characters 0 to 7. The escape code to define a new character is
7 '\e[LG' followed by one digit from 0 to 7, representing the character
11 top of the character to the bottom. On a 5x7 matrix, only the 5 lower
16 printf "\e[LG0010101050D1F0C04;" => 0 = [enter]
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| /Documentation/devicetree/bindings/pci/ |
| D | 83xx-512x-pci.txt | 12 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
14 /* IDSEL 0x0E -mini PCI */
15 0x7000 0x0 0x0 0x1 &ipic 18 0x8
16 0x7000 0x0 0x0 0x2 &ipic 18 0x8
17 0x7000 0x0 0x0 0x3 &ipic 18 0x8
18 0x7000 0x0 0x0 0x4 &ipic 18 0x8
20 /* IDSEL 0x0F - PCI slot */
21 0x7800 0x0 0x0 0x1 &ipic 17 0x8
22 0x7800 0x0 0x0 0x2 &ipic 18 0x8
23 0x7800 0x0 0x0 0x3 &ipic 17 0x8
[all …]
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| D | host-generic-pci.yaml | 94 property. If no "bus-range" is specified, this will be bus 0 (the
160 bus-range = <0x0 0x1>;
163 reg = <0x0 0x40000000 0x0 0x1000000>;
166 ranges = <0x01000000 0x0 0x01000000 0x0 0x01000000 0x0 0x00010000>,
167 <0x02000000 0x0 0x41000000 0x0 0x41000000 0x0 0x3f000000>;
169 #interrupt-cells = <0x1>;
172 interrupt-map = < 0x0 0x0 0x0 0x1 &gic 0x0 0x4 0x1>,
173 < 0x800 0x0 0x0 0x1 &gic 0x0 0x5 0x1>,
174 <0x1000 0x0 0x0 0x1 &gic 0x0 0x6 0x1>,
175 <0x1800 0x0 0x0 0x1 &gic 0x0 0x7 0x1>;
[all …]
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| D | axis,artpec6-pcie.txt | 28 reg = <0xf8050000 0x2000
29 0xf8040000 0x1000
30 0xc0000000 0x2000>;
36 ranges = <0x81000000 0 0 0xc0002000 0 0x00010000
38 0x82000000 0 0xc0012000 0xc0012000 0 0x1ffee000>;
40 bus-range = <0x00 0xff>;
44 interrupt-map-mask = <0 0 0 0x7>;
45 interrupt-map = <0 0 0 1 &intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
46 <0 0 0 2 &intc GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
47 <0 0 0 3 &intc GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
[all …]
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| D | cdns,cdns-pcie-host.yaml | 44 bus-range = <0x0 0xff>;
45 linux,pci-domain = <0>;
46 vendor-id = <0x17cd>;
47 device-id = <0x0200>;
49 reg = <0x0 0xfb000000 0x0 0x01000000>,
50 <0x0 0x41000000 0x0 0x00001000>;
53 ranges = <0x02000000 0x0 0x42000000 0x0 0x42000000 0x0 0x1000000>,
54 <0x01000000 0x0 0x43000000 0x0 0x43000000 0x0 0x0010000>;
55 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x1 0x00000000>;
57 #interrupt-cells = <0x1>;
[all …]
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| D | xgene-pci.txt | 35 reg = < 0x00 0x1f2b0000 0x0 0x00010000 /* Controller registers */
36 0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */
38 ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000 /* io */
39 0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000>; /* mem */
40 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
41 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
42 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
43 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x1
44 0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x1
45 0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x1
[all …]
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| D | mvebu-pci.txt | 23 0x82000000 0 r MBUS_ID(0xf0, 0x01) r 0 s
32 registers area. This range entry translates the '0x82000000 0 r' PCI
33 address into the 'MBUS_ID(0xf0, 0x01) r' CPU address, which is part
34 of the internal register window (as identified by MBUS_ID(0xf0,
35 0x01)).
39 0x8t000000 s 0 MBUS_ID(w, a) 0 1 0
79 value is 0.
99 bus-range = <0x00 0xff>;
103 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
104 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
[all …]
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| D | intel-gw-pcie.yaml | 96 reg = <0xd0e00000 0x1000>,
97 <0xd2000000 0x800000>,
98 <0xd0a41000 0x1000>;
100 linux,pci-domain = <0>;
102 bus-range = <0x00 0x08>;
104 interrupt-map-mask = <0 0 0 0x7>;
105 interrupt-map = <0 0 0 1 &ioapic1 27 1>,
106 <0 0 0 2 &ioapic1 28 1>,
107 <0 0 0 3 &ioapic1 29 1>,
108 <0 0 0 4 &ioapic1 30 1>;
[all …]
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| /Documentation/devicetree/bindings/opp/ |
| D | opp-v2-kryo-cpu.yaml | 43 '^opp-?[0-9]+$':
58 0: MSM8996, speedbin 0
65 0-3: unused
66 4: MSM8996SG, speedbin 0
72 0: IPQ8062
84 '^opp-microvolt-speed[0-9]+-pvs[0-9]+$': true
97 '^opp-?[0-9]+$':
113 #size-cells = <0>;
115 CPU0: cpu@0 {
118 reg = <0x0 0x0>;
[all …]
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| /Documentation/devicetree/bindings/phy/ |
| D | qcom,snps-eusb2-repeater.yaml | 31 const: 0
40 minimum: 0
42 default: 0
47 minimum: 0
54 minimum: 0
70 reg = <0x7 SPMI_USID>;
72 #size-cells = <0>;
76 reg = <0xfd00>;
77 #phy-cells = <0>;
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| /Documentation/devicetree/bindings/usb/ |
| D | chipidea,usb2-common.yaml | 54 AHBBRST at SBUSCFG, the range is from 0x0 to 0x7. This property is
59 minimum: 0x0
60 maximum: 0x7
68 is set to 0, if this property is missing the reset default of the
71 minimum: 0x0
72 maximum: 0x20
80 is set to 0, if this property is missing the reset default of the
83 minimum: 0x0
84 maximum: 0x20
92 required, empty <0> phandle should be specified.
[all …]
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| /Documentation/devicetree/bindings/net/ |
| D | brcm,mdio-mux-iproc.yaml | 43 reg = <0x66020000 0x250>;
45 #size-cells = <0>;
47 mdio@0 {
48 reg = <0x0>;
50 #size-cells = <0>;
52 pci_phy0: pci-phy@0 {
54 reg = <0x0>;
55 #phy-cells = <0>;
60 reg = <0x7>;
62 #size-cells = <0>;
[all …]
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| /Documentation/devicetree/bindings/bus/ |
| D | brcm,gisb-arb.yaml | 62 reg = <0xf0400000 0x800>;
63 interrupts = <0>, <2>;
65 brcm,gisb-arb-master-mask = <0x7>;
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| /Documentation/networking/device_drivers/ethernet/ti/ |
| D | tlan.rst | 31 0e11 ae32 Compaq Netelligent 10/100 TX PCI UTP
32 0e11 ae34 Compaq Netelligent 10 T PCI UTP
33 0e11 ae35 Compaq Integrated NetFlex 3/P
34 0e11 ae40 Compaq Netelligent Dual 10/100 TX PCI UTP
35 0e11 ae43 Compaq Netelligent Integrated 10/100 TX UTP
36 0e11 b011 Compaq Netelligent 10/100 TX Embedded UTP
37 0e11 b012 Compaq Netelligent 10 T/2 PCI UTP/Coax
38 0e11 b030 Compaq Netelligent 10/100 TX UTP
39 0e11 f130 Compaq NetFlex 3/P
40 0e11 f150 Compaq NetFlex 3/P
[all …]
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| /Documentation/devicetree/bindings/hwmon/ |
| D | ti,tmp401.yaml | 50 minimum: 0
85 #size-cells = <0>;
89 reg = <0x4c>;
95 #size-cells = <0>;
99 reg = <0x4c>;
101 ti,n-factor = <0x3b>;
102 ti,beta-compensation = <0x7>;
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