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/Documentation/devicetree/bindings/pci/
D83xx-512x-pci.txt12 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
14 /* IDSEL 0x0E -mini PCI */
15 0x7000 0x0 0x0 0x1 &ipic 18 0x8
16 0x7000 0x0 0x0 0x2 &ipic 18 0x8
17 0x7000 0x0 0x0 0x3 &ipic 18 0x8
18 0x7000 0x0 0x0 0x4 &ipic 18 0x8
20 /* IDSEL 0x0F - PCI slot */
21 0x7800 0x0 0x0 0x1 &ipic 17 0x8
22 0x7800 0x0 0x0 0x2 &ipic 18 0x8
23 0x7800 0x0 0x0 0x3 &ipic 17 0x8
[all …]
/Documentation/devicetree/bindings/thermal/
Dspear-thermal.txt12 reg = <0xfc000000 0x1000>;
13 st,thermal-flags = <0x7000>;
/Documentation/devicetree/bindings/mips/cavium/
Dciu.txt13 the CIU and may have a value of 0 or 1. The second cell is the bit
14 within the bank and may have a value between 0 and 63.
21 * 1) Controller register (0 or 1)
22 * 2) Bit within the register (0..63)
25 reg = <0x10700 0x00000000 0x0 0x7000>;
/Documentation/devicetree/bindings/phy/
Dmarvell,pxa1928-usb-phy.yaml25 const: 0
44 reg = <0x7000 0xe0>;
46 #phy-cells = <0>;
/Documentation/devicetree/bindings/remoteproc/
Dingenic,vpu.yaml66 reg = <0x132a0000 0x20>, /* AUX */
67 <0x132b0000 0x4000>, /* TCSM0 */
68 <0x132c0000 0xc000>, /* TCSM1 */
69 <0x132f0000 0x7000>; /* SRAM */
/Documentation/devicetree/bindings/media/
Dmediatek,mdp3-tdshp.yaml58 reg = <0x14007000 0x1000>;
59 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x7000 0x1000>;
/Documentation/devicetree/bindings/serial/
Dqcom,serial-geni-qcom.yaml44 pinctrl-0: true
76 reg = <0xa88000 0x7000>;
80 pinctrl-0 = <&qup_uart0_default>;
82 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
83 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
/Documentation/devicetree/bindings/net/
Drenesas,ethertsn.yaml67 enum: [0, 1800]
68 default: 0
71 enum: [0, 2000]
72 default: 0
102 reg = <0xe6460000 0x7000>,
103 <0xe6449000 0x500>;
118 #size-cells = <0>;
123 phy3: ethernet-phy@0 {
125 reg = <0>;
Dqcom,ipa.yaml222 qcom,local-pid = <0>;
244 iommus = <&apps_smmu 0x440 0x0>,
245 <&apps_smmu 0x442 0x0>;
246 reg = <0x1e40000 0x7000>,
247 <0x1e47000 0x2000>,
248 <0x1e04000 0x2c000>;
255 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
266 <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>,
267 <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>,
268 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>;
[all …]
Dti,k3-am654-cpsw-nuss.yaml19 The internal Communications Port Programming Interface (CPPI5) (Host port 0).
20 Host Port 0 CPPI Packet Streaming Interface interface supports 8 TX channels
27 Support for Audio/Video Bridging (P802.1Qav/D6.0)
31 IEEE P902.3br/D2.0 Interspersing Express Traffic
113 const: 0
169 "^mdio@[0-9a-f]+$":
176 "^cpts@[0-9a-f]+":
252 reg = <0x0 0x46000000 0x0 0x200000>;
254 ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>;
260 pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
[all …]
/Documentation/devicetree/bindings/soc/qcom/
Dqcom,geni-se.yaml67 "spi@[0-9a-f]+$":
75 "i2c@[0-9a-f]+$":
80 "serial@[0-9a-f]+$":
104 "spi@[0-9a-f]+$": false
105 "serial@[0-9a-f]+$": false
131 reg = <0 0x008c0000 0 0x6000>;
141 reg = <0 0xa94000 0 0x4000>;
146 pinctrl-0 = <&qup_1_i2c_5_active>;
149 #size-cells = <0>;
154 reg = <0 0xa88000 0 0x7000>;
[all …]
/Documentation/devicetree/bindings/display/mediatek/
Dmediatek,ethdr.yaml55 - description: video frontend 0 clock
57 - description: graphic frontend 0 clock
61 - description: video frontend 0 async clock
63 - description: graphic frontend 0 async clock
89 - description: video frontend 0 async reset
91 - description: graphic frontend 0 async reset
140 reg = <0 0x1c114000 0 0x1000>,
141 <0 0x1c115000 0 0x1000>,
142 <0 0x1c117000 0 0x1000>,
143 <0 0x1c119000 0 0x1000>,
[all …]
/Documentation/devicetree/bindings/pinctrl/
Dnuvoton,npcm7xx-pinctrl.txt32 reg = <0x0 0x80>;
34 gpio-ranges = <&pinctrl 0 0 32>;
113 <0> - slow
176 ranges = <0 0xf0010000 0x8000>;
181 reg = <0x0 0x80>;
183 gpio-ranges = <&pinctrl 0 0 32>;
191 reg = <0x7000 0x80>;
193 gpio-ranges = <&pinctrl 0 224 32>;
/Documentation/devicetree/bindings/powerpc/fsl/
Dinterlaken-lac.txt31 There is a full register set at 0x0000-0x0FFF (also known as the "hypervisor"
32 version), and a subset at 0x1000-0x1FFF. The former is a superset of the
45 IP Block Revision Register (IPBRR0) at offset 0x0BF8.
51 0x02000100 T4240
78 reg = <0x229000 0x1000>;
84 reg = <0x228000 0x1000>;
136 Register (IPBRR0), at offset 0x0BF8, and Y is the Minor version
161 #address-cells = <0x1>;
162 #size-cells = <0x1>;
164 ranges = <0x0 0xf 0xf4400000 0x20000>;
[all …]
/Documentation/admin-guide/laptops/
Dthinkpad-acpi.rst153 (output in hex format: 0xAAAABBCC), where:
211 events. If a key is "masked" (bit set to 0 in the mask), the firmware
240 echo 0xffffffff > /proc/acpi/ibm/hotkey -- enable all hot keys
241 echo 0 > /proc/acpi/ibm/hotkey -- disable all possible hot keys
262 Returns 0.
269 to this value. This is always 0x80c, because those are
276 0: returns -EPERM
323 0 and 25 Hz. Polling is only carried out when strictly
337 attribute will read 0 if the switch is in the "radios
345 will read 0 if the ThinkPad is in normal mode, and
[all …]
/Documentation/driver-api/media/drivers/
Dcx2341x-devel.rst23 ivtvctl -O min=0x02000000,max=0x020000ff
32 (Base Address Register 0). The addresses here are offsets relative to the
37 0x00000000-0x00ffffff Encoder memory space
38 0x00000000-0x0003ffff Encode.rom
44 0x01000000-0x01ffffff Decoder memory space
45 0x01000000-0x0103ffff Decode.rom
47 0x0114b000-0x0115afff Audio.rom (deprecated?)
49 0x02000000-0x0200ffff Register Space
54 The registers occupy the 64k space starting at the 0x02000000 offset from BAR0.
59 DMA Registers 0x000-0xff:
[all …]