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/Documentation/devicetree/bindings/pci/
D83xx-512x-pci.txt12 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
14 /* IDSEL 0x0E -mini PCI */
15 0x7000 0x0 0x0 0x1 &ipic 18 0x8
16 0x7000 0x0 0x0 0x2 &ipic 18 0x8
17 0x7000 0x0 0x0 0x3 &ipic 18 0x8
18 0x7000 0x0 0x0 0x4 &ipic 18 0x8
20 /* IDSEL 0x0F - PCI slot */
21 0x7800 0x0 0x0 0x1 &ipic 17 0x8
22 0x7800 0x0 0x0 0x2 &ipic 18 0x8
23 0x7800 0x0 0x0 0x3 &ipic 17 0x8
[all …]
/Documentation/devicetree/bindings/gpio/
Dbrcm,bcm63xx-gpio.yaml64 gpio@0 {
67 reg = <0x0 0x8>, <0x8 0x8>;
70 gpio-ranges = <&pinctrl 0 0 52>;
D8xxx_gpio.txt48 reg = <0xc00 0x100>;
50 interrupts = <74 0x8>;
59 reg = <0xd00 0x100>;
61 interrupts = <75 0x8>;
67 funkyfpga@0 {
/Documentation/devicetree/bindings/mfd/
Dbrcm,bcm63268-gpio-sysctl.yaml35 "^gpio@[0-9a-f]+$":
44 "^pinctrl@[0-9a-f]+$":
68 reg = <0x100000c0 0x80>;
69 ranges = <0 0x100000c0 0x80>;
71 gpio@0 {
74 reg = <0x0 0x8>, <0x8 0x8>;
77 gpio-ranges = <&pinctrl 0 0 52>;
83 reg = <0x10 0x4>, <0x18 0x8>, <0x38 0x4>;
Dbrcm,bcm6358-gpio-sysctl.yaml35 "^gpio@[0-9a-f]+$":
44 "^pinctrl@[0-9a-f]+$":
68 reg = <0xfffe0080 0x80>;
69 ranges = <0 0xfffe0080 0x80>;
71 gpio@0 {
74 reg = <0x0 0x8>, <0x8 0x8>;
77 gpio-ranges = <&pinctrl 0 0 40>;
83 reg = <0x18 0x4>;
Dbrcm,bcm6318-gpio-sysctl.yaml35 "^gpio@[0-9a-f]+$":
44 "^pinctrl@[0-9a-f]+$":
68 reg = <0x10000080 0x80>;
69 ranges = <0 0x10000080 0x80>;
71 gpio@0 {
74 reg = <0x0 0x8>, <0x8 0x8>;
77 gpio-ranges = <&pinctrl 0 0 50>;
83 reg = <0x18 0x10>, <0x54 0x18>;
Dbrcm,bcm6328-gpio-sysctl.yaml35 "^gpio@[0-9a-f]+$":
44 "^pinctrl@[0-9a-f]+$":
68 reg = <0x10000080 0x80>;
69 ranges = <0 0x10000080 0x80>;
71 gpio@0 {
74 reg = <0x0 0x8>, <0x8 0x8>;
77 gpio-ranges = <&pinctrl 0 0 32>;
83 reg = <0x18 0x10>;
Dbrcm,bcm6362-gpio-sysctl.yaml35 "^gpio@[0-9a-f]+$":
44 "^pinctrl@[0-9a-f]+$":
68 reg = <0x10000080 0x80>;
69 ranges = <0 0x10000080 0x80>;
71 gpio@0 {
74 reg = <0x0 0x8>, <0x8 0x8>;
77 gpio-ranges = <&pinctrl 0 0 48>;
83 reg = <0x18 0x10>, <0x38 0x4>;
Dbrcm,bcm6368-gpio-sysctl.yaml35 "^gpio@[0-9a-f]+$":
44 "^pinctrl@[0-9a-f]+$":
68 reg = <0x10000080 0x80>;
69 ranges = <0 0x10000080 0x80>;
71 gpio@0 {
74 reg = <0x0 0x8>, <0x8 0x8>;
77 gpio-ranges = <&pinctrl 0 0 38>;
83 reg = <0x18 0x4>, <0x38 0x4>;
/Documentation/devicetree/bindings/mips/cavium/
Dcib.txt26 reg = <0x10700 0x0000e000 0x0 0x8>, /* RAW */
27 <0x10700 0x0000e100 0x0 0x8>; /* EN */
Ddma-engine.txt19 reg = <0x11800 0x00000100 0x0 0x8>;
20 interrupts = <0 63>;
/Documentation/devicetree/bindings/regulator/
Dti-abb-regulator.txt17 - #address-cells: should be 0
18 - #size-cells: should be 0
32 0-bypass
56 from efuse-address to pick up ABB characteristics. Set to 0 if
60 + efuse maps to RBB mask. Set to 0 to ignore this.
64 Set to 0 to ignore this.
72 #address-cells = <0>;
73 #size-cells = <0>;
74 reg = <0x483072f0 0x8>, <0x48306818 0x4>;
76 ti,tranxdone-status-mask = <0x4000000>;
[all …]
/Documentation/devicetree/bindings/timer/
Darm,arch_timer_mmio.yaml63 '^frame@[0-9a-f]+$':
70 minimum: 0
104 ranges = <0 0xf0001000 0x1000>;
105 reg = <0xf0000000 0x1000>;
108 frame@0 {
109 frame-number = <0>;
110 interrupts = <0 13 0x8>,
111 <0 14 0x8>;
112 reg = <0x0000 0x1000>,
113 <0x1000 0x1000>;
[all …]
/Documentation/devicetree/bindings/powerpc/fsl/
Dmpc5121-psc.txt55 cell-index = <0>;
56 reg = <0x11000 0x100>;
57 interrupts = <40 0x8>;
66 reg = <0x11100 0x100>;
67 interrupts = <40 0x8>;
75 reg = <0x11f00 0x100>;
76 interrupts = <40 0x8>;
/Documentation/devicetree/bindings/mailbox/
Daltera-mailbox.txt18 reg = <0x100 0x8>;
26 reg = <0x200 0x8>;
37 device node and second argument is the channel index. It must be 0 (hardware
44 reg = <0x400 0x10>;
46 mboxes = <&mbox_tx 0>,
47 <&mbox_rx 0>;
/Documentation/devicetree/bindings/pinctrl/
Damlogic,meson-pinctrl-g12a-aobus.yaml24 "^bank@[0-9a-f]+$":
55 reg = <0x14 0x8>,
56 <0x1c 0x8>,
57 <0x24 0x14>;
61 gpio-ranges = <&ao_pinctrl 0 0 15>;
/Documentation/devicetree/bindings/net/
Dbrcm,bcmgenet.yaml56 "^mdio@[0-9a-f]+$":
82 reg = <0xf0b60000 0xfc4c>;
83 interrupts = <0x0 0x14 0x0>, <0x0 0x15 0x0>;
90 #size-cells = <0>;
91 reg = <0xe14 0x8>;
104 fixed-link = <1 0 1000 0 0>;
109 reg = <0xf0b80000 0xfc4c>;
110 interrupts = <0x0 0x16 0x0>, <0x0 0x17 0x0>;
115 #size-cells = <0>;
116 reg = <0xe14 0x8>;
[all …]
/Documentation/devicetree/bindings/net/can/
Dmpc5xxx-mscan.txt41 interrupts = <12 0x8>;
43 reg = <0x1300 0x80>;
48 interrupts = <13 0x8>;
50 reg = <0x1380 0x80>;
/Documentation/input/devices/
Dalps.rst32 E8-E6-E6-E6-E9. An ALPS touchpad should respond with either 00-00-0A or
33 00-00-64 if no buttons are pressed. The bits 0-2 of the first byte will be 1s
45 The new ALPS touchpads have an E7 signature of 73-03-50 or 73-03-0A but
94 byte 0: 0 0 YSGN XSGN 1 M R L
109 byte 0: 1 0 0 0 1 x9 x8 x7
110 byte 1: 0 x6 x5 x4 x3 x2 x1 x0
111 byte 2: 0 ? ? l r ? fin ges
112 byte 3: 0 ? ? ? ? y9 y8 y7
113 byte 4: 0 y6 y5 y4 y3 y2 y1 y0
114 byte 5: 0 z6 z5 z4 z3 z2 z1 z0
[all …]
/Documentation/devicetree/bindings/remoteproc/
Damlogic,meson-mx-ao-arc.yaml79 reg = <0x1c 0x8>, <0x38 0x8>;
/Documentation/devicetree/bindings/clock/
Dxgene.txt50 Default is 0.
51 - csr-mask : CSR reset mask bit. Default is 0xF.
53 Default is 0x8.
54 - enable-mask : CSR enable mask bit. Default is 0xF.
56 Default is 0x0.
57 - divider-width : Width of the divider register. Default is 0.
58 - divider-shift : Bit shift of the divider register. Default is 0.
65 clocks = <&refclk 0>;
67 reg = <0x0 0x17000100 0x0 0x1000>;
69 type = <0>;
[all …]
/Documentation/devicetree/bindings/media/i2c/
Dpanasonic,amg88xx.txt4 8x8 10Hz video which consists of thermal datapoints
16 reg = <0x69>;
/Documentation/gpu/amdgpu/display/
Dtrace-groups-table.csv2 INFO, 0x1
3 IRQ SVC, 0x2
4 VBIOS, 0x4
5 REGISTER, 0x8
6 PHY DBG, 0x10
7 PSR, 0x20
8 AUX, 0x40
9 SMU, 0x80
10 MALL, 0x100
11 ABM, 0x200
[all …]
/Documentation/devicetree/bindings/cache/
Dsocionext,uniphier-system-cache.yaml69 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>;
70 interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>;
72 cache-size = <0x140000>;
82 reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, <0x506c0000 0x400>;
83 interrupts = <0 190 4>, <0 191 4>;
85 cache-size = <0x200000>;
94 reg = <0x500c8000 0x2000>, <0x503c8100 0x8>, <0x506c8000 0x400>;
95 interrupts = <0 174 4>, <0 175 4>;
97 cache-size = <0x200000>;
/Documentation/devicetree/bindings/opp/
Dti,omap-opp-supply.yaml10 OMAP5, DRA7, and AM57 families of SoCs have Class 0 AVS eFuse
31 pattern: '^opp-supply(@[0-9a-f]+)?$'
37 - description: OMAP5+ optimized voltages in efuse(Class 0) VDD along with
94 reg = <0x4a003b20 0x8>;
97 <1060000 0x0>,
98 <1160000 0x4>,
99 <1210000 0x8>;

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