Searched +full:0 +full:x80 (Results 1 – 25 of 154) sorted by relevance
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| /Documentation/devicetree/bindings/dma/ |
| D | mediatek,uart-dma.yaml | 92 reg = <0 0x11000400 0 0x80>,
93 <0 0x11000480 0 0x80>,
94 <0 0x11000500 0 0x80>,
95 <0 0x11000580 0 0x80>,
96 <0 0x11000600 0 0x80>,
97 <0 0x11000680 0 0x80>,
98 <0 0x11000700 0 0x80>,
99 <0 0x11000780 0 0x80>,
100 <0 0x11000800 0 0x80>,
101 <0 0x11000880 0 0x80>,
[all …]
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| /Documentation/devicetree/bindings/powerpc/fsl/ |
| D | dma.txt | 14 - cell-index : controller index. 0 for controller @ 0x8100
21 - cell-index : DMA channel index starts at 0.
33 reg = <0x82a8 4>;
34 ranges = <0 0x8100 0x1a4>;
37 cell-index = <0>;
38 dma-channel@0 {
40 cell-index = <0>;
41 reg = <0 0x80>;
48 reg = <0x80 0x80>;
55 reg = <0x100 0x80>;
[all …]
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| /Documentation/devicetree/bindings/pwm/ |
| D | pwm-tipwmss.txt | 25 reg = <0x48300000 0x10>;
29 ranges = <0x48300100 0x48300100 0x80 /* ECAP */
30 0x48300180 0x48300180 0x80 /* EQEP */
31 0x48300200 0x48300200 0x80>; /* EHRPWM */
38 reg = <0x48300000 0x10>;
42 ranges = <0x48300100 0x48300100 0x80 /* ECAP */
43 0x48300180 0x48300180 0x80 /* EQEP */
44 0x48300200 0x48300200 0x80>; /* EHRPWM */
51 reg = <0x4843e000 0x30>;
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| /Documentation/devicetree/bindings/power/ |
| D | ti-smartreflex.txt | 30 reg = <0x4a0db000 0x80>;
37 reg = <0x4a0dd000 0x80>;
44 reg = <0x4a0d9000 0x80>;
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| /Documentation/devicetree/bindings/pci/ |
| D | xgene-pci.txt | 35 reg = < 0x00 0x1f2b0000 0x0 0x00010000 /* Controller registers */
36 0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */
38 ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000 /* io */
39 0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000>; /* mem */
40 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
41 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
42 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
43 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x1
44 0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x1
45 0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x1
[all …]
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| D | xilinx-versal-cpm.yaml | 55 const: 0
87 interrupts = <0 72 4>;
89 interrupt-map-mask = <0 0 0 7>;
90 interrupt-map = <0 0 0 1 &pcie_intc_0 0>,
91 <0 0 0 2 &pcie_intc_0 1>,
92 <0 0 0 3 &pcie_intc_0 2>,
93 <0 0 0 4 &pcie_intc_0 3>;
94 bus-range = <0x00 0xff>;
95 ranges = <0x02000000 0x0 0xe0010000 0x0 0xe0010000 0x0 0x10000000>,
96 <0x43000000 0x80 0x00000000 0x80 0x00000000 0x0 0x80000000>;
[all …]
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| D | xgene-pci-msi.txt | 8 - reg: physical base address (0x79000000) and length (0x900000) for controller
13 interrupt number 0x10 to 0x1f.
27 reg = <0x00 0x79000000 0x0 0x900000>;
28 interrupts = <0x0 0x10 0x4>
29 <0x0 0x11 0x4>
30 <0x0 0x12 0x4>
31 <0x0 0x13 0x4>
32 <0x0 0x14 0x4>
33 <0x0 0x15 0x4>
34 <0x0 0x16 0x4>
[all …]
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| D | layerscape-pcie-gen4.txt | 30 reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
31 0x80 0x00000000 0x0 0x00001000>; /* configuration space */
43 bus-range = <0x0 0xff>;
45 ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>;
47 interrupt-map-mask = <0 0 0 7>;
48 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
49 <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
50 <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
51 <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
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| /Documentation/devicetree/bindings/soc/fsl/cpm_qe/ |
| D | fsl,qe-ic.yaml | 43 reg = <0x80 0x80>;
46 interrupts = <95 2 0 0 94 2 0 0>;
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| D | fsl,qe.yaml | 106 reg = <0xe0100000 0x480>;
107 ranges = <0 0xe0100000 0x00100000>;
110 brg-frequency = <0>;
111 bus-frequency = <0x179a7b00>;
113 0x04 0x05 0x0c 0x0d 0x14 0x15 0x1c 0x1d
114 0x24 0x25 0x2c 0x2d 0x34 0x35 0x88 0x89
115 0x98 0x99 0xa8 0xa9 0xb8 0xb9 0xc8 0xc9
116 0xd8 0xd9 0xe8 0xe9>;
120 reg = <0x80 0x80>;
123 interrupts = <95 2 0 0 94 2 0 0>;
[all …]
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| /Documentation/firmware-guide/acpi/ |
| D | method-tracing.rst | 47 # echo "0xXXXXXXXX" > trace_debug_layer
48 # echo "0xYYYYYYYY" > trace_debug_level
55 # echo "0xXXXXXXXX" > trace_debug_layer
56 # echo "0xYYYYYYYY" > trace_debug_level
64 # echo "0xXXXXXXXX" > trace_debug_layer
65 # echo "0xYYYYYYYY" > trace_debug_level
70 0xXXXXXXXX/0xYYYYYYYY
85 …[ 0.186427] exdebug-0398 ex_trace_point : Method Begin [0xf58394d8:\_SB.PCI0.LPCB.ECOK…
86 [ 0.186630] exdebug-0398 ex_trace_point : Opcode Begin [0xf5905c88:If] execution.
87 [ 0.186820] exdebug-0398 ex_trace_point : Opcode Begin [0xf5905cc0:LEqual] execution.
[all …]
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| /Documentation/devicetree/bindings/display/ |
| D | brcm,bcm2711-hdmi.yaml | 117 reg = <0x7ef00700 0x300>,
118 <0x7ef00300 0x200>,
119 <0x7ef00f00 0x80>,
120 <0x7ef00f80 0x80>,
121 <0x7ef01b00 0x200>,
122 <0x7ef01f00 0x400>,
123 <0x7ef00200 0x80>,
124 <0x7ef04300 0x100>,
125 <0x7ef20000 0x100>;
137 resets = <&dvp 0>;
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| /Documentation/devicetree/bindings/iommu/ |
| D | sprd,iommu.yaml | 19 const: 0
45 reg = <0x63000800 0x80>;
46 #iommu-cells = <0>;
52 reg = <0x62300300 0x80>;
53 #iommu-cells = <0>;
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| /Documentation/hwmon/ |
| D | gl518sm.rst | 6 * Genesys Logic GL518SM release 0x00
10 Addresses scanned: I2C 0x2c and 0x2d
12 * Genesys Logic GL518SM release 0x80
16 Addresses scanned: I2C 0x2c and 0x2d
31 For the revision 0x00 chip, the in0, in1, and in2 values (+5V, +3V,
35 two revision of this chip, which we call revision 0x00 and 0x80. Revision
36 0x80 chips support the reading of all voltages and revision 0x00 only
64 a resolution of 0.019 volt. Note that revision 0x00 chips do not support
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| /Documentation/devicetree/bindings/spi/ |
| D | spi-sunplus-sp7021.yaml | 55 - pinctrl-0
64 reg = <0x9c002d80 0x80>, <0x9c002e00 0x80>;
73 clocks = <&clkc 0x32>;
74 resets = <&rstc 0x22>;
76 pinctrl-0 = <&pins_spi0>;
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| /Documentation/devicetree/bindings/net/can/ |
| D | cc770.txt | 12 to map the registers of the controller. The size is usually 0x80.
25 If not specified or if the specified value is 0, the CLKOUT pin
49 reg = <3 0x100 0x80>;
50 interrupts = <2 0>;
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| D | mpc5xxx-mscan.txt | 41 interrupts = <12 0x8>;
43 reg = <0x1300 0x80>;
48 interrupts = <13 0x8>;
50 reg = <0x1380 0x80>;
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | sunplus,sp7021-intc.yaml | 54 reg = <0x9c000780 0x80>, <0x9c000a80 0x80>;
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| /Documentation/admin-guide/nfs/ |
| D | pnfs-block-server.rst | 27 how to translate the device into a serial number from SCSI EVPD 0x80::
37 EVPD=`sg_inq --page=0x80 ${DEV} | \
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| /Documentation/devicetree/bindings/power/supply/ |
| D | cw2015_battery.yaml | 61 #size-cells = <0>;
65 reg = <0x62>;
67 0x17 0x67 0x80 0x73 0x6E 0x6C 0x6B 0x63
68 0x77 0x51 0x5C 0x58 0x50 0x4C 0x48 0x36
69 0x15 0x0C 0x0C 0x19 0x5B 0x7D 0x6F 0x69
70 0x69 0x5B 0x0C 0x29 0x20 0x40 0x52 0x59
71 0x57 0x56 0x54 0x4F 0x3B 0x1F 0x7F 0x17
72 0x06 0x1A 0x30 0x5A 0x85 0x93 0x96 0x2D
73 0x48 0x77 0x9C 0xB3 0x80 0x52 0x94 0xCB
74 0x2F 0x00 0x64 0xA5 0xB5 0x11 0xF0 0x11
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| /Documentation/devicetree/bindings/mailbox/ |
| D | fsl,mu.yaml | 82 0 - TX channel with 32bit transmit register and IRQ transmit
158 reg = <0x5d1b0000 0x10000>;
168 reg = <0x445b0000 0x10000>;
177 reg = <0x445b1000 0x400>;
178 ranges = <0x0 0x445b1000 0x400>;
182 scmi-sram-section@0 {
184 reg = <0x0 0x80>;
189 reg = <0x80 0x80>;
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| /Documentation/devicetree/bindings/mfd/ |
| D | qriox.txt | 14 board-control@1,0 {
16 reg = <1 0 0x80>;
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| D | aspeed-lpc.yaml | 16 peripheral devices, replacing the use of the ISA bus in the age of PCI[0]. The
60 "^lpc-ctrl@[0-9a-f]+$":
95 "^reset-controller@[0-9a-f]+$":
121 "^lpc-snoop@[0-9a-f]+$":
152 "^uart-routing@[0-9a-f]+$":
173 reg = <0x1e789000 0x1000>;
177 ranges = <0x0 0x1e789000 0x1000>;
181 reg = <0x80 0x80>;
189 reg = <0x98 0x4>;
195 reg = <0x90 0x8>;
[all …]
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| /Documentation/gpu/amdgpu/display/ |
| D | trace-groups-table.csv | 2 INFO, 0x1
3 IRQ SVC, 0x2
4 VBIOS, 0x4
5 REGISTER, 0x8
6 PHY DBG, 0x10
7 PSR, 0x20
8 AUX, 0x40
9 SMU, 0x80
10 MALL, 0x100
11 ABM, 0x200
[all …]
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| /Documentation/fault-injection/ |
| D | nvme-fault-injection.rst | 33 name fault_inject, interval 1, probability 100, space 0, times 1
34 CPU: 0 PID: 0 Comm: swapper/0 Not tainted 4.15.0-rc8+ #2
39 dump_stack+0x5c/0x7d
40 should_fail+0x148/0x170
41 nvme_should_fail+0x2f/0x50 [nvme_core]
42 nvme_process_cq+0xe7/0x1d0 [nvme]
43 nvme_irq+0x1e/0x40 [nvme]
44 __handle_irq_event_percpu+0x3a/0x190
45 handle_irq_event_percpu+0x30/0x70
46 handle_irq_event+0x36/0x60
[all …]
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