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/Documentation/devicetree/bindings/mtd/
Dflctl-nand.txt26 reg = <0xe6a30000 0x100>;
27 interrupts = <0x0d80>;
35 system@0 {
37 reg = <0x0 0x8000000>;
42 reg = <0x8000000 0x10000000>;
47 reg = <0x18000000 0x8000000>;
Dtechnologic,nand.yaml39 reg = <0x60000000 0x8000000>;
41 #size-cells = <0>;
42 nand@0 {
43 reg = <0>;
Datmel-nand.txt38 device (always 0)
39 3rd entry: the memory region size (always 0x800000)
67 reg = <0x70000000 0x8000000>;
72 reg = <0xffffc070 0x490>,
73 <0xffffc500 0x100>;
81 reg = <0x10000000 0x10000000
82 0x40000000 0x30000000>;
83 ranges = <0x0 0x0 0x10000000 0x10000000
84 0x1 0x0 0x40000000 0x10000000
85 0x2 0x0 0x50000000 0x10000000
[all …]
/Documentation/devicetree/bindings/pci/
Drcar-pci-ep.yaml79 reg = <0xfe000000 0x80000>,
80 <0xfe100000 0x100000>,
81 <0xfe200000 0x200000>,
82 <0x30000000 0x8000000>,
83 <0x38000000 0x8000000>;
Dti,am65-pci-ep.yaml66 reg = <0x5500000 0x1000>,
67 <0x5501000 0x1000>,
68 <0x10000000 0x8000000>,
69 <0x5506000 0x1000>;
72 ti,syscon-pcie-mode = <&scm_conf 0x4060>;
Dmobiveil-pcie.txt49 reg = <0xa0000000 0x00001000>,
50 <0xb0000000 0x00010000>,
51 <0xff000000 0x00200000>,
52 <0xb0010000 0x00001000>;
60 bus-range = <0x00000000 0x000000ff>;
64 interrupts = < 0 89 4 >;
65 interrupt-map-mask = <0 0 0 7>;
66 interrupt-map = <0 0 0 0 &pci_express 0>,
67 <0 0 0 1 &pci_express 1>,
68 <0 0 0 2 &pci_express 2>,
[all …]
Dfsl,imx6q-pcie-ep.yaml134 reg = <0x33800000 0x100000>,
135 <0x18000000 0x8000000>,
136 <0x33900000 0x100000>,
137 <0x33b00000 0x100000>;
Dmediatek-pcie.txt32 where N starting from 0 to one less than the number of root ports.
80 reg = <0 0x1a000000 0 0x1000>;
88 reg = <0 0x1a140000 0 0x1000>, /* PCIe shared registers */
89 <0 0x1a142000 0 0x1000>, /* Port0 registers */
90 <0 0x1a143000 0 0x1000>, /* Port1 registers */
91 <0 0x1a144000 0 0x1000>; /* Port2 registers */
96 interrupt-map-mask = <0xf800 0 0 0>;
97 interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,
98 <0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>,
99 <0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
[all …]
/Documentation/gpu/amdgpu/display/
Dtrace-groups-table.csv2 INFO, 0x1
3 IRQ SVC, 0x2
4 VBIOS, 0x4
5 REGISTER, 0x8
6 PHY DBG, 0x10
7 PSR, 0x20
8 AUX, 0x40
9 SMU, 0x80
10 MALL, 0x100
11 ABM, 0x200
[all …]
/Documentation/devicetree/bindings/bus/
Dmvebu-mbus.txt65 pcie-mem-aperture = <0xe0000000 0x8000000>;
66 pcie-io-aperture = <0xe8000000 0x100000>;
73 reg = <0x20000 0x100>, <0x20180 0x20>, <0x20250 0x8>;
87 0xSIAA0000 0x00oooooo
91 S = 0x0 for a MBus valid window
92 S = 0xf for a non-valid window (see below)
94 If S = 0x0, then:
99 If S = 0xf, then:
105 (S = 0x0), an address decoding window is allocated. On the other side,
106 entries for translation that do not correspond to valid windows (S = 0xf)
[all …]
/Documentation/devicetree/bindings/spi/
Dspi-zynqmp-qspi.yaml61 interrupts = <0 15 4>;
63 reg = <0x0 0xff0f0000 0x0 0x1000>,
64 <0x0 0xc0000000 0x0 0x8000000>;
Datmel,quadspi.yaml62 const: 0
82 reg = <0xf0020000 0x100>, <0xd0000000 0x8000000>;
88 #size-cells = <0>;
90 pinctrl-0 = <&pinctrl_spi0_default>;
92 flash@0 {
95 reg = <0>;
/Documentation/devicetree/bindings/memory-controllers/
Dti-aemif.txt25 first address cell and it may accept values 0..N-1
76 it can be in range [0-3]. For compatible
105 Minimum value is 1 (0 treated as 1).
110 Minimum value is 1 (0 treated as 1).
117 Minimum value is 1 (0 treated as 1).
122 Minimum value is 1 (0 treated as 1).
127 Minimum value is 1 (0 treated as 1).
134 Minimum value is 1 (0 treated as 1).
145 clocks = <&clkaemif 0>;
148 reg = <0x21000A00 0x00000100>;
[all …]
Dti,gpmc.yaml82 <cs-number> 0 <physical address of mapping> <size>
84 - description: NAND bank 0
85 - description: NOR/SRAM bank 0
97 0 - NAND_fifoevent
109 0 maps to GPMC_WAIT0 pin.
126 "@[0-7],[a-f0-9]+$":
163 reg = <0x50000000 0x2000>;
167 dmas = <&edma 52 0>;
173 ranges = <0 0 0x08000000 0x10000000>; /* CS0 @addr 0x8000000, size 0x10000000 */
179 nand@0,0 {
[all …]
/Documentation/devicetree/bindings/fpga/
Dxlnx,fpga-selectmap.yaml79 reg = <0x8000000 0x4>;
/Documentation/devicetree/bindings/watchdog/
Dsnps,dw-wdt.yaml70 default: [0x0001000 0x0002000 0x0004000 0x0008000
71 0x0010000 0x0020000 0x0040000 0x0080000
72 0x0100000 0x0200000 0x0400000 0x0800000
73 0x1000000 0x2000000 0x4000000 0x8000000]
88 reg = <0xffd02000 0x1000>;
89 interrupts = <0 171 4>;
97 reg = <0xffd02000 0x1000>;
98 interrupts = <0 171 4>;
101 snps,watchdog-tops = <0x000000FF 0x000001FF 0x000003FF
102 0x000007FF 0x0000FFFF 0x0001FFFF
[all …]
/Documentation/devicetree/bindings/leds/
Dregister-bit-led.yaml26 pattern: '^led@[0-9a-f]+,[0-9a-f]{1,2}$'
41 [ 0x1, 0x2, 0x4, 0x8, 0x10, 0x20, 0x40, 0x80, 0x100, 0x200, 0x400, 0x800,
42 0x1000, 0x2000, 0x4000, 0x8000, 0x10000, 0x20000, 0x40000, 0x80000,
43 0x100000, 0x200000, 0x400000, 0x800000, 0x1000000, 0x2000000, 0x4000000,
44 0x8000000, 0x10000000, 0x20000000, 0x40000000, 0x80000000 ]
64 reg = <0x10000000 0x1000>;
67 ranges = <0x0 0x10000000 0x1000>;
69 led@8,0 {
71 reg = <0x08 0x04>;
72 offset = <0x08>;
[all …]
/Documentation/devicetree/bindings/misc/
Dfsl,qoriq-mc.yaml58 Registers BRR1 and BRR2 at offset 0x0BF8 and 0x0BFC in
81 0x0 - MC portals
82 0x1 - QBMAN portals
140 const: 0
161 reg = <0x0c000000 0x40>, /* MC portal base */
162 <0x08340000 0x40000>; /* MC control reg */
164 * Region type 0x0 - MC portals
165 * Region type 0x1 - QBMAN portals
167 ranges = <0x0 0x0 0x8 0x0c000000 0x4000000
168 0x1 0x0 0x8 0x18000000 0x8000000>;
[all …]
/Documentation/devicetree/bindings/regulator/
Dti-abb-regulator.txt17 - #address-cells: should be 0
18 - #size-cells: should be 0
32 0-bypass
56 from efuse-address to pick up ABB characteristics. Set to 0 if
60 + efuse maps to RBB mask. Set to 0 to ignore this.
64 Set to 0 to ignore this.
72 #address-cells = <0>;
73 #size-cells = <0>;
74 reg = <0x483072f0 0x8>, <0x48306818 0x4>;
76 ti,tranxdone-status-mask = <0x4000000>;
[all …]
/Documentation/admin-guide/
Dramoops.rst29 Typically the default value of ``mem_type=0`` should be used as that sets the pstore
46 ``max_reason`` should be set to 1 (KMSG_DUMP_PANIC). Setting this to 0
71 mem=128M ramoops.mem_address=0x8000000 ramoops.ecc=1
84 reg = <0 0x8f000000 0 0x100000>;
85 record-size = <0x4000>;
86 console-size = <0x4000>;
168 0 ffffffff8101ea64 ffffffff8101bcda native_apic_mem_read <- disconnect_bsp_APIC+0x6a/0xc0
169 0 ffffffff8101ea44 ffffffff8101bcf6 native_apic_mem_write <- disconnect_bsp_APIC+0x86/0xc0
170 0 ffffffff81020084 ffffffff8101a4b5 hpet_disable <- native_machine_shutdown+0x75/0x90
171 0 ffffffff81005f94 ffffffff8101a4bb iommu_shutdown_noop <- native_machine_shutdown+0x7b/0x90
[all …]
/Documentation/devicetree/bindings/cache/
Dl2c2x0.yaml72 without setup latency control should use a value of 0.
77 minimum: 0
83 should use 0. Controllers without separate read and write Tag RAM latency
89 minimum: 0
131 enum: [0, 1]
137 enum: [0, 1]
143 enum: [0, 1]
149 enum: [0, 1]
154 enum: [0, 1, 2, 3, 4, 5, 6, 7, 15, 23, 31]
185 Data prefetch. Value: <0> (forcibly disable), <1>
[all …]