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/Documentation/devicetree/bindings/pci/
Dxgene-pci.txt35 reg = < 0x00 0x1f2b0000 0x0 0x00010000 /* Controller registers */
36 0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */
38 ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000 /* io */
39 0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000>; /* mem */
40 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
41 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
42 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
43 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x1
44 0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x1
45 0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x1
[all …]
Dxgene-pci-msi.txt8 - reg: physical base address (0x79000000) and length (0x900000) for controller
13 interrupt number 0x10 to 0x1f.
27 reg = <0x00 0x79000000 0x0 0x900000>;
28 interrupts = <0x0 0x10 0x4>
29 <0x0 0x11 0x4>
30 <0x0 0x12 0x4>
31 <0x0 0x13 0x4>
32 <0x0 0x14 0x4>
33 <0x0 0x15 0x4>
34 <0x0 0x16 0x4>
[all …]
D83xx-512x-pci.txt12 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
14 /* IDSEL 0x0E -mini PCI */
15 0x7000 0x0 0x0 0x1 &ipic 18 0x8
16 0x7000 0x0 0x0 0x2 &ipic 18 0x8
17 0x7000 0x0 0x0 0x3 &ipic 18 0x8
18 0x7000 0x0 0x0 0x4 &ipic 18 0x8
20 /* IDSEL 0x0F - PCI slot */
21 0x7800 0x0 0x0 0x1 &ipic 17 0x8
22 0x7800 0x0 0x0 0x2 &ipic 18 0x8
23 0x7800 0x0 0x0 0x3 &ipic 17 0x8
[all …]
Dbrcm,stb-pcie.yaml190 reg = <0x0 0x7d500000 0x9310>;
198 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
199 interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH
200 0 0 0 2 &gicv2 GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH
201 0 0 0 3 &gicv2 GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH
202 0 0 0 4 &gicv2 GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
206 ranges = <0x02000000 0x0 0xf8000000 0x6 0x00000000 0x0 0x04000000>;
207 dma-ranges = <0x42000000 0x1 0x00000000 0x0 0x40000000 0x0 0x80000000>,
208 <0x42000000 0x1 0x80000000 0x3 0x00000000 0x0 0x80000000>;
210 brcm,scb-sizes = <0x0000000080000000 0x0000000080000000>;
[all …]
Dxilinx-versal-cpm.yaml55 const: 0
87 interrupts = <0 72 4>;
89 interrupt-map-mask = <0 0 0 7>;
90 interrupt-map = <0 0 0 1 &pcie_intc_0 0>,
91 <0 0 0 2 &pcie_intc_0 1>,
92 <0 0 0 3 &pcie_intc_0 2>,
93 <0 0 0 4 &pcie_intc_0 3>;
94 bus-range = <0x00 0xff>;
95 ranges = <0x02000000 0x0 0xe0010000 0x0 0xe0010000 0x0 0x10000000>,
96 <0x43000000 0x80 0x00000000 0x80 0x00000000 0x0 0x80000000>;
[all …]
Dcdns,cdns-pcie-ep.yaml41 reg = <0x0 0xfc000000 0x0 0x01000000>,
42 <0x0 0x80000000 0x0 0x40000000>;
Dv3-v360epc-pci.txt18 each be exactly 256MB (0x10000000) in size.
38 reg = <0x62000000 0x10000>, <0x61000000 0x01000000>;
42 bus-range = <0x00 0xff>;
43 ranges = 0x01000000 0 0x00000000 /* I/O space @00000000 */
44 0x60000000 0 0x01000000 /* 16 MiB @ LB 60000000 */
45 0x02000000 0 0x40000000 /* non-prefectable memory @40000000 */
46 0x40000000 0 0x10000000 /* 256 MiB @ LB 40000000 1:1 */
47 0x42000000 0 0x50000000 /* prefetchable memory @50000000 */
48 0x50000000 0 0x10000000>; /* 256 MiB @ LB 50000000 1:1 */
49 dma-ranges = <0x02000000 0 0x20000000 /* EBI memory space */
[all …]
/Documentation/devicetree/bindings/mtd/partitions/
Dpartition.yaml63 maximum: 0x80000000
80 maximum: 0x80000000
96 maximum: 0x80000000
131 reg = <0x100000 0xf00000>;
132 align-size = <0x1000>;
133 align-end = <0x10000>;
138 reg = <0x200000 0x100000>;
139 align = <0x4000>;
/Documentation/gpu/amdgpu/display/
Dtrace-groups-table.csv2 INFO, 0x1
3 IRQ SVC, 0x2
4 VBIOS, 0x4
5 REGISTER, 0x8
6 PHY DBG, 0x10
7 PSR, 0x20
8 AUX, 0x40
9 SMU, 0x80
10 MALL, 0x100
11 ABM, 0x200
[all …]
/Documentation/devicetree/bindings/clock/
Dclps711x-clock.txt17 reg = <0x80000000 0xc000>;
/Documentation/devicetree/bindings/gpio/
Dgpio-clps711x.txt11 0 = active high
25 reg = <0x80000000 0x1>, <0x80000040 0x1>;
/Documentation/devicetree/bindings/
Dnuma.txt29 /* numa node 0 */
30 numa-node-id = <0>;
65 0_______20______1
76 0 -> 1 = 20
79 3 -> 0 = 20
80 0 -> 2 = 40
87 distance-matrix = <0 0 10>,
88 <0 1 20>,
89 <0 2 40>,
90 <0 3 20>,
[all …]
/Documentation/devicetree/bindings/crypto/
Darm,cryptocell.yaml51 reg = <0x80000000 0x10000>;
/Documentation/devicetree/bindings/spi/
Dsocionext,f-ospi.yaml46 reg = <0x80000000 0x1000>;
47 clocks = <&clks 0>;
50 #size-cells = <0>;
52 flash@0 {
54 reg = <0>;
Dnuvoton,npcm-fiu.txt17 - #size-cells : should be 0.
25 - pinctrl-0 : phandle referencing pin configuration of the device.
34 fiu0 represent fiu 0 controller
39 fiu0 represent fiu 0 controller
48 #size-cells = <0>;
49 reg = <0xfb000000 0x1000>, <0x80000000 0x10000000>;
53 pinctrl-0 = <&spi3_pins>;
54 flash@0 {
/Documentation/devicetree/bindings/rng/
Dmicrosoft,vmgenid.yaml45 reg = <0x80000000 0x1000>;
/Documentation/devicetree/bindings/soc/intel/
Dintel,hps-copy-engine.yaml39 reg = <0x80000000 0x60000000>,
40 <0xf9000000 0x00100000>;
44 ranges = <0x00000000 0x00000000 0xf9000000 0x00001000>;
46 dma-controller@0 {
48 reg = <0x00000000 0x00000000 0x00001000>;
/Documentation/devicetree/bindings/interrupt-controller/
Dcirrus,clps711x-intc.txt38 reg = <0x80000000 0x4000>;
/Documentation/devicetree/bindings/hwmon/
Dadi,axi-fan-control.yaml52 #address-cells = <0x2>;
53 #size-cells = <0x1>;
57 reg = <0x0 0x80000000 0x10000>;
59 interrupts = <0 110 0>;
/Documentation/devicetree/bindings/net/
Dcpsw.txt37 driven low so that cpsw slave 0 and phy data
73 reg = <0x4A100000 0x1000>;
74 interrupts = <55 0x4>;
78 bd_ram_size = <0x2000>;
80 mac_control = <0x20>;
82 active_slave = <0>;
83 cpts_clock_mult = <0x80000000>;
87 cpsw_emac0: slave@0 {
88 phy_id = <&davinci_mdio>, <0>;
92 phys = <&phy_gmii_sel 1 0>;
[all …]
/Documentation/devicetree/bindings/mtd/
Dcadence-nand-controller.txt11 - #size-cells : should be 0.
27 - reg: shall contain the native Chip Select ids from 0 to max supported by
38 #size-cells = <0>;
39 reg = <0x60000000 0x10000>, <0x80000000 0x10000>;
43 interrupts = <2 0>;
44 nand@0 {
45 reg = <0>;
/Documentation/devicetree/bindings/perf/
Dmarvell-cn10k-tad.yaml58 reg = <0x87e2 0x80000000 0x0 0x1000>;
60 marvell,tad-page-size = <0x1000>;
61 marvell,tad-pmu-page-size = <0x1000>;
/Documentation/staging/
Dcrc32.rst9 remainder computed on the message+CRC is 0. This latter approach
15 - We're working in binary, so the digits are only 0 and 1, and
38 back into range. In binary, this is easy - it has to be either 0 or 1,
48 for (i = 0; i < input_bits; i++) {
49 multiple = remainder & 0x80000000 ? CRCPOLY : 0;
68 for (i = 0; i < input_bits; i++) {
70 multiple = (remainder & 0x80000000) ? CRCPOLY : 0;
76 for (i = 0; i < input_bits; i++) {
78 multiple = (remainder & 1) ? CRCPOLY : 0;
91 for (i = 0; i < input_bytes; i++) {
[all …]
/Documentation/devicetree/bindings/bus/
Darm,integrator-ap-lm.yaml15 determine if a logic module is connected at index 0, 1, 2 or 3. The logic
35 "^bus(@[0-9a-f]*)?$":
37 and are named with bus. The first module is at 0xc0000000, the second
38 at 0xd0000000 and so on until the top of the memory of the system at
39 0xffffffff. All information about the memory used by the module is
55 ranges = <0xc0000000 0xc0000000 0x40000000>;
60 ranges = <0x00000000 0xc0000000 0x10000000>;
61 /* The Logic Modules sees the Core Module 0 RAM @80000000 */
62 dma-ranges = <0x00000000 0x80000000 0x10000000>;
68 reg = <0x00100000 0x1000>;
[all …]
/Documentation/arch/xtensa/
Dmmu.rst16 - RASID is 0x04030201 (reset state).
28 After step 2, we jump to virtual address in the range 0x40000000..0x5fffffff
29 or 0x00000000..0x1fffffff, depending on whether the kernel was loaded below
30 0x40000000 or above. That address corresponds to next instruction to execute
32 The scheme below assumes that the kernel is loaded below 0x40000000.
49 The default location of IO peripherals is above 0xf0000000. This may be changed
75 | Userspace | 0x00000000 TASK_SIZE
76 +------------------+ 0x40000000
78 | Page table | XCHAL_PAGE_TABLE_VADDR 0x80000000 XCHAL_PAGE_TABLE_SIZE
80 | KASAN shadow map | KASAN_SHADOW_START 0x80400000 KASAN_SHADOW_SIZE
[all …]

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