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Searched +full:0 +full:x90000000 (Results 1 – 8 of 8) sorted by relevance

/Documentation/devicetree/bindings/pci/
D83xx-512x-pci.txt12 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
14 /* IDSEL 0x0E -mini PCI */
15 0x7000 0x0 0x0 0x1 &ipic 18 0x8
16 0x7000 0x0 0x0 0x2 &ipic 18 0x8
17 0x7000 0x0 0x0 0x3 &ipic 18 0x8
18 0x7000 0x0 0x0 0x4 &ipic 18 0x8
20 /* IDSEL 0x0F - PCI slot */
21 0x7800 0x0 0x0 0x1 &ipic 17 0x8
22 0x7800 0x0 0x0 0x2 &ipic 18 0x8
23 0x7800 0x0 0x0 0x3 &ipic 17 0x8
[all …]
Dapple,pcie.yaml114 reg = <0x6 0x90000000 0x0 0x1000000>,
115 <0x6 0x80000000 0x0 0x100000>,
116 <0x6 0x81000000 0x0 0x4000>,
117 <0x6 0x82000000 0x0 0x4000>,
118 <0x6 0x83000000 0x0 0x4000>;
130 iommu-map = <0x100 &dart0 1 1>,
131 <0x200 &dart1 1 1>,
132 <0x300 &dart2 1 1>;
133 iommu-map-mask = <0xff00>;
135 bus-range = <0 3>;
[all …]
Dnvidia,tegra20-pcie.txt27 - cell 0 specifies the bus and device numbers of the root port:
30 - cell 1 denotes the upper 32 address bits and should be 0
45 - 0x81000000: I/O memory region
46 - 0x82000000: non-prefetchable memory region
47 - 0xc2000000: prefetchable memory region
73 - pinctrl-0: phandle for the default/active state of pin configurations.
104 - If lanes 0 to 3 are used:
150 - Root port 0 uses 4 lanes, root port 1 is unused.
158 "pcie-N": where N ranges from 0 to the value specified in nvidia,num-lanes.
171 reg = <0x80003000 0x00000800 /* PADS registers */
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/Documentation/devicetree/bindings/gpio/
Dlsi,zevio-gpio.yaml40 reg = <0x90000000 0x1000>;
/Documentation/devicetree/bindings/mips/cavium/
Dbootbus.txt52 - cavium,pages: A cell specifying the PAGES parameter (0 = 8 bytes, 1
71 reg = <0x11800 0x00000000 0x0 0x200>;
76 ranges = <0 0 0x0 0x1f400000 0xc00000>,
77 <1 0 0x10000 0x30000000 0>,
78 <2 0 0x10000 0x40000000 0>,
79 <3 0 0x10000 0x50000000 0>,
80 <4 0 0x0 0x1d020000 0x10000>,
81 <5 0 0x0 0x1d040000 0x10000>,
82 <6 0 0x0 0x1d050000 0x10000>,
83 <7 0 0x10000 0x90000000 0>;
[all …]
/Documentation/arch/xtensa/
Dmmu.rst16 - RASID is 0x04030201 (reset state).
28 After step 2, we jump to virtual address in the range 0x40000000..0x5fffffff
29 or 0x00000000..0x1fffffff, depending on whether the kernel was loaded below
30 0x40000000 or above. That address corresponds to next instruction to execute
32 The scheme below assumes that the kernel is loaded below 0x40000000.
49 The default location of IO peripherals is above 0xf0000000. This may be changed
75 | Userspace | 0x00000000 TASK_SIZE
76 +------------------+ 0x40000000
78 | Page table | XCHAL_PAGE_TABLE_VADDR 0x80000000 XCHAL_PAGE_TABLE_SIZE
80 | KASAN shadow map | KASAN_SHADOW_START 0x80400000 KASAN_SHADOW_SIZE
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/Documentation/arch/x86/
Dpat.rst117 as step 0 above and also track the usage of those pages and use set_memory_wb()
182 uncached-minus @ 0x7fadf000-0x7fae0000
183 uncached-minus @ 0x7fb19000-0x7fb1a000
184 uncached-minus @ 0x7fb1a000-0x7fb1b000
185 uncached-minus @ 0x7fb1b000-0x7fb1c000
186 uncached-minus @ 0x7fb1c000-0x7fb1d000
187 uncached-minus @ 0x7fb1d000-0x7fb1e000
188 uncached-minus @ 0x7fb1e000-0x7fb25000
189 uncached-minus @ 0x7fb25000-0x7fb26000
190 uncached-minus @ 0x7fb26000-0x7fb27000
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/Documentation/devicetree/bindings/cpu/
Didle-states.yaml102 between 0 and infinite time, until a wake-up event occurs.
127 wakeup-delay = exit-latency + max(entry-latency - (now - entry-timestamp), 0)
167 0| 1 time(ms)
172 The graph curve with X-axis values = { x | 0 < x < 1ms } has a steep slope
444 #size-cells = <0>;
447 cpu@0 {
450 reg = <0x0 0x0>;
459 reg = <0x0 0x1>;
468 reg = <0x0 0x100>;
477 reg = <0x0 0x101>;
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