| /Documentation/devicetree/bindings/sound/ |
| D | qcom,pm8916-wcd-analog-codec.yaml | 110 reg = <0x1 SPMI_USID>;
112 #size-cells = <0>;
116 reg = <0xf000>;
120 interrupts = <0x1 0xf0 0x0 IRQ_TYPE_NONE>,
121 <0x1 0xf0 0x1 IRQ_TYPE_NONE>,
122 <0x1 0xf0 0x2 IRQ_TYPE_NONE>,
123 <0x1 0xf0 0x3 IRQ_TYPE_NONE>,
124 <0x1 0xf0 0x4 IRQ_TYPE_NONE>,
125 <0x1 0xf0 0x5 IRQ_TYPE_NONE>,
126 <0x1 0xf0 0x6 IRQ_TYPE_NONE>,
[all …]
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| /Documentation/devicetree/bindings/pci/ |
| D | mvebu-pci.txt | 23 0x82000000 0 r MBUS_ID(0xf0, 0x01) r 0 s
32 registers area. This range entry translates the '0x82000000 0 r' PCI
33 address into the 'MBUS_ID(0xf0, 0x01) r' CPU address, which is part
34 of the internal register window (as identified by MBUS_ID(0xf0,
35 0x01)).
39 0x8t000000 s 0 MBUS_ID(w, a) 0 1 0
79 value is 0.
99 bus-range = <0x00 0xff>;
103 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
104 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
[all …]
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| /Documentation/devicetree/bindings/bus/ |
| D | mvebu-mbus.txt | 65 pcie-mem-aperture = <0xe0000000 0x8000000>;
66 pcie-io-aperture = <0xe8000000 0x100000>;
73 reg = <0x20000 0x100>, <0x20180 0x20>, <0x20250 0x8>;
87 0xSIAA0000 0x00oooooo
91 S = 0x0 for a MBus valid window
92 S = 0xf for a non-valid window (see below)
94 If S = 0x0, then:
99 If S = 0xf, then:
105 (S = 0x0), an address decoding window is allocated. On the other side,
106 entries for translation that do not correspond to valid windows (S = 0xf)
[all …]
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| /Documentation/devicetree/bindings/phy/ |
| D | phy-cadence-torrent.yaml | 30 const: 0
77 '^phy@[0-3]$':
85 minimum: 0
95 const: 0
118 enum: [0, 1, 2]
119 default: 0
160 reg = <0xf0 0xfb500000 0x0 0x00100000>,
161 <0xf0 0xfb030a00 0x0 0x00000040>;
163 resets = <&phyrst 0>;
168 #size-cells = <0>;
[all …]
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| D | phy-miphy28lp.txt | 56 reg = <0x9b22000 0xff>,
57 <0x9b09000 0xff>,
58 <0x9b04000 0xff>;
63 st,syscfg = <0x114 0x818 0xe0 0xec>;
71 reg = <0x9b2a000 0xff>,
72 <0x9b19000 0xff>,
73 <0x9b14000 0xff>;
78 st,syscfg = <0x118 0x81c 0xe4 0xf0>;
87 reg = <0x8f95000 0xff>,
88 <0x8f90000 0xff>;
[all …]
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| /Documentation/devicetree/bindings/spi/ |
| D | spi-orion.txt | 19 chip-select lines 0 through 7 respectively.
37 #size-cells = <0>;
38 cell-index = <0>;
39 reg = <0x10600 0x28>;
47 #size-cells = <0>;
48 cell-index = <0>;
49 reg = <MBUS_ID(0xf0, 0x01) 0x10600 0x28>, /* control */
50 <MBUS_ID(0x01, 0x1e) 0 0xffffffff>, /* CS0 */
51 <MBUS_ID(0x01, 0x5e) 0 0xffffffff>, /* CS1 */
52 <MBUS_ID(0x01, 0x9e) 0 0xffffffff>, /* CS2 */
[all …]
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| /Documentation/devicetree/bindings/soc/microchip/ |
| D | microchip,sparx5-cpu-syscon.yaml | 41 reg = <0x6 0x00000000 0xd0>;
46 mux-reg-masks = <0x88 0xf0>;
|
| /Documentation/fault-injection/ |
| D | nvme-fault-injection.rst | 33 name fault_inject, interval 1, probability 100, space 0, times 1
34 CPU: 0 PID: 0 Comm: swapper/0 Not tainted 4.15.0-rc8+ #2
39 dump_stack+0x5c/0x7d
40 should_fail+0x148/0x170
41 nvme_should_fail+0x2f/0x50 [nvme_core]
42 nvme_process_cq+0xe7/0x1d0 [nvme]
43 nvme_irq+0x1e/0x40 [nvme]
44 __handle_irq_event_percpu+0x3a/0x190
45 handle_irq_event_percpu+0x30/0x70
46 handle_irq_event+0x36/0x60
[all …]
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| /Documentation/devicetree/bindings/board/ |
| D | fsl,fpga-qixis-i2c.yaml | 45 #size-cells = <0>;
49 reg = <0x66>;
56 #size-cells = <0>;
61 reg = <0x66>;
66 mux-reg-masks = <0x54 0xf0>; /* 0: reg 0x54, bits 7:4 */
|
| /Documentation/devicetree/bindings/display/msm/ |
| D | qcom,msm8998-dpu.yaml | 64 reg = <0x0c901000 0x8f000>,
65 <0x0c9a8e00 0xf0>,
66 <0x0c9b0000 0x2008>,
67 <0x0c9b8000 0x1040>;
78 interrupts = <0>;
84 #size-cells = <0>;
86 port@0 {
87 reg = <0>;
|
| D | qcom,msm8998-mdss.yaml | 39 "^display-controller@[0-9a-f]+$":
47 "^dsi@[0-9a-f]+$":
57 "^phy@[0-9a-f]+$":
79 reg = <0x0c900000 0x1000>;
93 iommus = <&mmss_smmu 0>;
100 reg = <0x0c901000 0x8f000>,
101 <0x0c9a8e00 0xf0>,
102 <0x0c9b0000 0x2008>,
103 <0x0c9b8000 0x1040>;
114 interrupts = <0>;
[all …]
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| /Documentation/w1/masters/ |
| D | w1-uart.rst | 25 the baud-rate 9600, i.e. 104.2 us per bit. The transmitted byte 0xf0 over
32 115200, i.e. 8.7 us per bit. The transmitted byte 0x80 is used for a
33 Write-0 operation (low time 69.6us) and the byte 0xff for Read-0, Read-1
|
| /Documentation/devicetree/bindings/power/supply/ |
| D | cw2015_battery.yaml | 61 #size-cells = <0>;
65 reg = <0x62>;
67 0x17 0x67 0x80 0x73 0x6E 0x6C 0x6B 0x63
68 0x77 0x51 0x5C 0x58 0x50 0x4C 0x48 0x36
69 0x15 0x0C 0x0C 0x19 0x5B 0x7D 0x6F 0x69
70 0x69 0x5B 0x0C 0x29 0x20 0x40 0x52 0x59
71 0x57 0x56 0x54 0x4F 0x3B 0x1F 0x7F 0x17
72 0x06 0x1A 0x30 0x5A 0x85 0x93 0x96 0x2D
73 0x48 0x77 0x9C 0xB3 0x80 0x52 0x94 0xCB
74 0x2F 0x00 0x64 0xA5 0xB5 0x11 0xF0 0x11
|
| /Documentation/devicetree/bindings/pwm/ |
| D | microchip,corepwm.yaml | 52 default: 0
66 default: 0
79 microchip,sync-update-mask = /bits/ 32 <0>;
81 reg = <0x41000000 0xF0>;
|
| /Documentation/devicetree/bindings/gpu/host1x/ |
| D | nvidia,tegra210-nvdec.yaml | 20 pattern: "^nvdec@[0-9a-f]*$"
70 default: 0xf0
94 reg = <0x15480000 0x40000>;
|
| /Documentation/devicetree/bindings/net/ |
| D | marvell-bt-8xxx.txt | 52 #size-cells = <0>;
60 0x37 0x01 0x1c 0x00 0xff 0xff 0xff 0xff 0x01 0x7f 0x04 0x02
61 0x00 0x00 0xba 0xce 0xc0 0xc6 0x2d 0x00 0x00 0x00 0x00 0x00
62 0x00 0x00 0xf0 0x00>;
63 marvell,wakeup-pin = /bits/ 16 <0x0d>;
64 marvell,wakeup-gap-ms = /bits/ 16 <0x64>;
72 #size-cells = <0>;
80 marvell,wakeup-pin = /bits/ 16 <0x0d>;
81 marvell,wakeup-gap-ms = /bits/ 16 <0x64>;
|
| /Documentation/devicetree/bindings/display/bridge/ |
| D | cdns,mhdp8546.yaml | 64 port@0:
90 - port@0
137 reg = <0xf0 0xfb000000 0x0 0x1000000>;
146 #size-cells = <0>;
148 port@0 {
149 reg = <0>;
|
| /Documentation/input/devices/ |
| D | elantech.rst | 69 (TouchPadOff=0) will also disable the buttons associated with the touchpad.
99 By echoing "0" to this file all debugging will be turned OFF.
113 By echoing "0" to this file parity checking will be turned OFF. Any
128 Sets crc_enabled to 0/1. The name "crc_enabled" is the official name of
138 "0" or "1" to this file will set the state to "0" or "1".
143 To detect the hardware version, read the version number as param[0].param[1].param[2]::
164 Probably all the versions with param[0] <= 01 can be considered as
179 echo -n 0x16 > reg_10
183 bit 7 6 5 4 3 2 1 0
197 bit 7 6 5 4 3 2 1 0
[all …]
|
| D | atarikbd.rst | 32 is obtained by ORing 0x80 with the make code.
34 The special codes 0xF6 through 0xFF are reserved for use as follows:
39 0xF6 status report
40 0xF7 absolute mouse position record
41 0xF8-0xFB relative mouse position records (lsbs determined by
43 0xFC time-of-day
44 0xFD joystick report (both sticks)
45 0xFE joystick 0 event
46 0xFF joystick 1 event
114 LEFT=0x74 & RIGHT=0x75).
[all …]
|
| /Documentation/userspace-api/media/cec/ |
| D | cec-ioc-g-mode.rst | 80 :header-rows: 0
81 :stub-columns: 0
87 - 0x0
93 - 0x1
100 - 0x2
116 :header-rows: 0
117 :stub-columns: 0
123 - 0x00
128 - 0x10
136 - 0x20
[all …]
|
| /Documentation/trace/ |
| D | histogram.rst | 226 field:unsigned short common_type; offset:0; size:2; signed:0;
227 field:unsigned char common_flags; offset:2; size:1; signed:0;
228 field:unsigned char common_preempt_count; offset:3; size:1; signed:0;
231 field:unsigned long call_site; offset:8; size:8; signed:0;
232 field:const void * ptr; offset:16; size:8; signed:0;
233 field:size_t bytes_req; offset:24; size:8; signed:0;
234 field:size_t bytes_alloc; offset:32; size:8; signed:0;
235 field:gfp_t gfp_flags; offset:40; size:4; signed:0;
288 Dropped: 0
305 allowed for the table (normally 0, but if not a hint that you may
[all …]
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| /Documentation/userspace-api/media/dvb/ |
| D | legacy_dvb_osd.rst | 71 :stub-columns: 0
91 | Returns 0 on success.
98 | BitPerPixel[2/4/8]{color&0x0F},
99 | mix[0..15]{color&0xF0}
102 | Returns 0 on success,
113 | Returns 0 on success.
122 | Returns 0 on success.
130 - | Sets all pixel to color 0.
131 | Returns 0 on success.
140 | Returns 0 on success.
[all …]
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| /Documentation/driver-api/mtd/ |
| D | nand_ecc.rst | 34 if the data over which the parity is calculated is 1 and the parity bit = 0
35 if the data over which the parity is calculated is 0. So the total
45 byte 0: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 rp0 rp2 rp4 ... rp14
78 - rp0 is the parity of all even bytes (0, 2, 4, 6, ... 252, 254)
80 - rp2 is the parity of all bytes 0, 1, 4, 5, 8, 9, ...
85 so rp4 calculates parity over bytes 0, 1, 2, 3, 8, 9, 10, 11, 16, ...)
105 ECC Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
107 ECC 0 rp07 rp06 rp05 rp04 rp03 rp02 rp01 rp00
120 Attempt 0
126 for (i = 0; i < 256; i++)
[all …]
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| /Documentation/usb/ |
| D | gadget_hid.rst | 29 .subclass = 0, /* No subclass */
34 0x05, 0x01, /* USAGE_PAGE (Generic Desktop) */
35 0x09, 0x06, /* USAGE (Keyboard) */
36 0xa1, 0x01, /* COLLECTION (Application) */
37 0x05, 0x07, /* USAGE_PAGE (Keyboard) */
38 0x19, 0xe0, /* USAGE_MINIMUM (Keyboard LeftControl) */
39 0x29, 0xe7, /* USAGE_MAXIMUM (Keyboard Right GUI) */
40 0x15, 0x00, /* LOGICAL_MINIMUM (0) */
41 0x25, 0x01, /* LOGICAL_MAXIMUM (1) */
42 0x75, 0x01, /* REPORT_SIZE (1) */
[all …]
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| /Documentation/arch/s390/ |
| D | vfio-ap.rst | 27 functions. There can be from 0 to 256 adapters assigned to an LPAR. Adapters
29 the linux host. Each adapter is identified by a number from 0 to 255; however,
38 4 and 10 (0x0a) are assigned to the LPAR, the AP bus will create the following
54 identified by a number from 0 to 255; however, the maximum domain number is
76 significant bit, correspond to domains 0-255.
90 AP bus module is loaded. For example, if adapters 4 and 10 (0x0a) and usage
91 domains 6 and 71 (0x47) are assigned to the LPAR, the AP bus will create the
96 /sys/devices/ap/card0a/0a.0006
97 /sys/devices/ap/card0a/0a.0047
104 /sys/bus/ap/devices/[0a.0006]
[all …]
|