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/Documentation/devicetree/bindings/power/supply/
Dmaxim,max17201.yaml49 #size-cells = <0>;
53 reg = <0x36>, <0xb>;
Dsbs,sbs-battery.yaml37 default: 0
44 default: 0
74 #size-cells = <0>;
78 reg = <0xb>;
/Documentation/RCU/
Dlockdep-splat.rst30 rcu_scheduler_active = 1, debug_locks = 0
32 #0: (&shost->scan_mutex){+.+.}, at: [<ffffffff8145efca>]
33 scsi_scan_host_selected+0x5a/0x150
35 elevator_exit+0x22/0x60
37 cfq_exit_queue+0x43/0x190
40 Pid: 1552, comm: scsi_scan_6 Not tainted 3.0.0-rc5 #17
42 [<ffffffff810abb9b>] lockdep_rcu_dereference+0xbb/0xc0
43 [<ffffffff812b6139>] __cfq_exit_single_io_context+0xe9/0x120
44 [<ffffffff812b626c>] cfq_exit_queue+0x7c/0x190
45 [<ffffffff812a5046>] elevator_exit+0x36/0x60
[all …]
/Documentation/devicetree/bindings/i2c/
Dgoogle,cros-ec-i2c-tunnel.yaml44 #size-cells = <0>;
46 cros-ec@0 {
48 reg = <0>;
50 interrupts = <99 0>;
55 #size-cells = <0>;
57 google,remote-bus = <0>;
61 reg = <0xb>;
Di2c-arb-gpio-challenge.yaml117 #size-cells = <0>;
121 reg = <0xb>;
127 reg = <0x1e>;
131 pinctrl-0 = <&ec_irq>;
/Documentation/devicetree/bindings/dma/
Dti-edma.txt25 <&tptc_phandle TC_priority_number>. The highest priority is 0.
86 reg = <0x49000000 0x10000>;
93 ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 7>, <&edma_tptc2 0>;
100 dma-channel-mask = <0xffffffff /* Channel 0-31 */
101 0xffffe007>; /* Channel 32-63 */
107 reg = <0x49800000 0x100000>;
115 reg = <0x49900000 0x100000>;
123 reg = <0x49a00000 0x100000>;
131 reg = <0x53100000 0x200>;
134 dmas = <&edma 36 0>;
[all …]
/Documentation/trace/coresight/
Dultrasoc-smb.rst38 BIT(0) is zero value which means the buffer is empty.
58 ReadWrite, 0x0, 0x95100000, 0x951FFFFF, 0x0, 0x100000) \
60 ReadWrite, 0x0, 0x50000000, 0x53FFFFFF, 0x0, 0x4000000) \
66 0, \
72 Package() {0x8, 0, \_SB.S00.SL11.CL28.F008, 0}, \
73 Package() {0x9, 0, \_SB.S00.SL11.CL29.F009, 0}, \
74 Package() {0xa, 0, \_SB.S00.SL11.CL2A.F010, 0}, \
75 Package() {0xb, 0, \_SB.S00.SL11.CL2B.F011, 0}, \
76 Package() {0xc, 0, \_SB.S00.SL11.CL2C.F012, 0}, \
77 Package() {0xd, 0, \_SB.S00.SL11.CL2D.F013, 0}, \
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/Documentation/devicetree/bindings/mfd/
Dkontron,sl28cpld.yaml30 const: 0
41 "^gpio(@[0-9a-f]+)?$":
44 "^hwmon(@[0-9a-f]+)?$":
47 "^interrupt-controller(@[0-9a-f]+)?$":
50 "^pwm(@[0-9a-f]+)?$":
53 "^watchdog(@[0-9a-f]+)?$":
69 #size-cells = <0>;
73 reg = <0x4a>;
75 #size-cells = <0>;
79 reg = <0x4>;
[all …]
/Documentation/sound/cards/
Demu10k1-jack.rst30 /usr/local/bin/jackd -R -dalsa -r48000 -p64 -n2 -D -Chw:0,2 -Phw:0,3 -S
60 capture_1 asio14 FXBUS2(0xe)
61 capture_2 asio15 FXBUS2(0xf)
62 capture_3 asio0 FXBUS2(0x0)
63 ~capture_4 Center EXTOUT(0x11) // mapped to by Center
64 ~capture_5 LFE EXTOUT(0x12) // mapped to by LFE
65 capture_6 asio3 FXBUS2(0x3)
66 capture_7 asio4 FXBUS2(0x4)
67 capture_8 asio5 FXBUS2(0x5)
68 capture_9 asio6 FXBUS2(0x6)
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/Documentation/devicetree/bindings/interrupt-controller/
Dmsi.txt86 reg = <0xa 0xf00>;
93 reg = <0xb 0xf00>;
101 reg = <0xc 0xf00>;
108 dev@0 {
109 reg = <0x0 0xf00>;
117 reg = <0x1 0xf00>;
123 msi-parent = <&msi_a>, <&msi_b 0x17>;
127 reg = <0x2 0xf00>;
133 msi-parent = <&msi_a>, <&msi_b 0x17>, <&msi_c 0x53>;
/Documentation/devicetree/bindings/pci/
Dpci-iommu.txt13 * Bits [2:0] are the Function number.
56 reg = <0xa 0x1>;
62 reg = <0xf 0x1>;
70 iommu-map = <0x0 &iommu 0x0 0x10000>;
83 reg = <0xa 0x1>;
89 reg = <0xf 0x1>;
97 iommu-map = <0x0 &iommu 0x0 0x10000>;
98 iommu-map-mask = <0xfff8>;
111 reg = <0xa 0x1>;
117 reg = <0xf 0x1>;
[all …]
Dpci-msi.txt13 * Bits [2:0] are the Function number.
67 reg = <0xa 0x1>;
74 reg = <0xf 0x1>;
82 msi-map = <0x0 &msi_a 0x0 0x10000>,
95 reg = <0xa 0x1>;
102 reg = <0xf 0x1>;
110 msi-map = <0x0 &msi_a 0x0 0x100>,
111 msi-map-mask = <0xff>
124 reg = <0xa 0x1>;
131 reg = <0xf 0x1>;
[all …]
/Documentation/devicetree/bindings/clock/
Dsilabs,si5341.txt39 - reg: i2c device address, usually 0x74
41 The first value is "0" for outputs, "1" for synthesizers.
62 - silabs,xaxb-ext-clk: When present, indicates that the XA/XB pins are used
71 - #size-cells: shall be set to 0.
102 #clock-cells = <0>;
109 reg = <0x74>;
113 #size-cells = <0>;
121 out@0 {
122 reg = <0>;
156 clocks = <&si5341 0 7>; /* Output 7 */
[all …]
/Documentation/devicetree/bindings/net/dsa/
Dmarvell,mv88e6xxx.yaml27 marvell,mv88e6085: This switch uses base address 0x10.
33 marvell,mv88e6190: This switch uses base address 0x00.
38 marvell,mv88e6250: This switch uses base address 0x08 or 0x18.
114 #size-cells = <0>;
116 ethernet-switch@0 {
118 reg = <0>;
123 #size-cells = <0>;
125 sw_phy0: ethernet-phy@0 {
126 reg = <0x0>;
130 reg = <0x1>;
[all …]
/Documentation/bpf/standardization/
Dinstruction-set.rst197 the source register number (0-10), except where otherwise specified
201 destination register number (0-10), unless otherwise specified
220 07 0 1 00 00 44 33 22 11 r1 += 0x11223344 // little
222 07 1 0 00 00 11 22 33 44 r1 += 0x11223344 // big
277 LD 0x0 non-standard load operations `Load and store instructions`_
278 LDX 0x1 load into register operations `Load and store instructions`_
279 ST 0x2 store from immediate operations `Load and store instructions`_
280 STX 0x3 store from register operations `Load and store instructions`_
281 ALU 0x4 32-bit arithmetic operations `Arithmetic and jump instructions`_
282 JMP 0x5 64-bit jump operations `Arithmetic and jump instructions`_
[all …]
/Documentation/devicetree/bindings/
Dnuma.txt29 /* numa node 0 */
30 numa-node-id = <0>;
65 0_______20______1
76 0 -> 1 = 20
79 3 -> 0 = 20
80 0 -> 2 = 40
87 distance-matrix = <0 0 10>,
88 <0 1 20>,
89 <0 2 40>,
90 <0 3 20>,
[all …]
/Documentation/admin-guide/perf/
Dnvidia-pmu.rst41 * Count event id 0x0 in socket 0::
43 perf stat -a -e nvidia_scf_pmu_0/event=0x0/
45 * Count event id 0x0 in socket 1::
47 perf stat -a -e nvidia_scf_pmu_1/event=0x0/
73 * Count event id 0x0 from the GPU/CPU connected with socket 0::
75 perf stat -a -e nvidia_nvlink_c2c0_pmu_0/event=0x0/
77 * Count event id 0x0 from the GPU/CPU connected with socket 1::
79 perf stat -a -e nvidia_nvlink_c2c0_pmu_1/event=0x0/
81 * Count event id 0x0 from the GPU/CPU connected with socket 2::
83 perf stat -a -e nvidia_nvlink_c2c0_pmu_2/event=0x0/
[all …]
/Documentation/arch/sparc/oradax/
Ddax-hv-api.txt79 Only version 0 CCBs are available.
108 … Version 0 and 1 CCBs are available. Only version 0 CCBs may use Huffman encoded data, whereas only
115 …node indicates N interrupts available, the guest may use any value from 0 to N - 1 (inclusive) in …
140 [31:28] CCB version. For API version 2.0: set to 1 if CCB uses OZIP encoding; set to 0 if the…
141 uses Huffman encoding; otherwise either 0 or 1. For API version 1.0: always set to 0.
148 0x00 No Operation (No-op) or Sync
149 0x01 Extract
150 0x02 Scan Value
151 0x12 Inverted Scan Value
152 0x03 Scan Range
[all …]
/Documentation/trace/
Dftrace.rst56 tracefs /sys/kernel/tracing tracefs defaults 0 0
111 ring buffer is enabled. Echo 0 into this file to disable
118 set this file to "0". User space can re-enable tracing by
161 or cleared by writing a "1" or "0" respectively into the
180 Only active when the file contains a number greater than 0.
192 0 - means to wake up as soon as there is any data in the ring buffer.
476 If the option "record-cmd" is set to "0", then comms of tasks
622 if (trace_fd < 0)
973 # irqsoff latency trace v1.1.5 on 3.8.0-test+
975 # latency: 259 us, #4/4, CPU#2 | (M:preempt VP:0, KP:0, SP:0 HP:0 #P:4)
[all …]
/Documentation/virt/kvm/
Dapi.rst148 You probably want to use 0 as machine type.
178 address used by the VM. The IPA_Bits is encoded in bits[7-0] of the
188 0 Implies default size, 40bits (for backward compatibility)
214 :Returns: 0 on success; -1 on error
228 __u32 indices[0];
256 :Returns: 0 if unsupported; 1 (or some other positive integer) if supported
261 Generally 0 means no and 1 means yes, but some extensions may report
304 The vcpu id is an integer in the range [0, max_vcpu_id).
348 :Returns: 0 on success, -1 on error
363 since the last call to this ioctl. Bit 0 is the first page in the
[all …]