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Searched +full:0 +full:xb0000000 (Results 1 – 10 of 10) sorted by relevance

/Documentation/devicetree/bindings/pci/
Dxlnx,xdma-host.yaml50 - const: 0
51 - const: 0
52 - const: 0
68 const: 0
124 reg = <0x0 0xa0000000 0x0 0x10000000>;
125 ranges = <0x2000000 0x0 0xb0000000 0x0 0xb0000000 0x0 0x1000000>,
126 <0x43000000 0x5 0x0 0x5 0x0 0x0 0x1000000>;
135 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
136 interrupt-map = <0 0 0 1 &pcie_intc_0 0>,
137 <0 0 0 2 &pcie_intc_0 1>,
[all …]
Dmobiveil-pcie.txt49 reg = <0xa0000000 0x00001000>,
50 <0xb0000000 0x00010000>,
51 <0xff000000 0x00200000>,
52 <0xb0010000 0x00001000>;
60 bus-range = <0x00000000 0x000000ff>;
64 interrupts = < 0 89 4 >;
65 interrupt-map-mask = <0 0 0 7>;
66 interrupt-map = <0 0 0 0 &pci_express 0>,
67 <0 0 0 1 &pci_express 1>,
68 <0 0 0 2 &pci_express 2>,
[all …]
Dnvidia,tegra20-pcie.txt27 - cell 0 specifies the bus and device numbers of the root port:
30 - cell 1 denotes the upper 32 address bits and should be 0
45 - 0x81000000: I/O memory region
46 - 0x82000000: non-prefetchable memory region
47 - 0xc2000000: prefetchable memory region
73 - pinctrl-0: phandle for the default/active state of pin configurations.
104 - If lanes 0 to 3 are used:
150 - Root port 0 uses 4 lanes, root port 1 is unused.
158 "pcie-N": where N ranges from 0 to the value specified in nvidia,num-lanes.
171 reg = <0x80003000 0x00000800 /* PADS registers */
[all …]
/Documentation/devicetree/bindings/mips/cavium/
Dciu3.txt24 #address-cells = <0>;
26 reg = <0x10100 0x00000000 0x0 0xb0000000>;
/Documentation/devicetree/bindings/memory-controllers/
Dti,da8xx-ddrctl.yaml34 reg = <0xb0000000 0xe8>;
/Documentation/devicetree/bindings/mtd/
Dsamsung,s5pv210-onenand.yaml20 - description: OneNAND interface nCE[0]
52 reg = <0xb0600000 0x2000>,
53 <0xb0000000 0x20000>,
54 <0xb0040000 0x20000>;
60 #size-cells = <0>;
62 nand@0 {
63 reg = <0>;
/Documentation/devicetree/bindings/clock/
Dxlnx,clocking-wizard.yaml22 - xlnx,clocking-wizard-v6.0
71 reg = <0xb0000000 0x10000>;
/Documentation/devicetree/bindings/spi/
Dcdns,xspi.yaml80 #size-cells = <0>;
82 reg = <0x0 0xa0010000 0x0 0x1040>,
83 <0x0 0xb0000000 0x0 0x1000>,
84 <0x0 0xa0020000 0x0 0x100>;
86 interrupts = <0 90 IRQ_TYPE_LEVEL_HIGH>;
89 flash@0 {
92 reg = <0>;
/Documentation/devicetree/bindings/arm/
Dxen.txt13 Region 0 is reserved for mapping grant table, it must be always present.
47 reg = <0 0xb0000000 0 0x20000>;
48 interrupts = <1 15 0xf08>;
50 xen,uefi-system-table = <0xXXXXXXXX>;
51 xen,uefi-mmap-start = <0xXXXXXXXX>;
52 xen,uefi-mmap-size = <0xXXXXXXXX>;
53 xen,uefi-mmap-desc-size = <0xXXXXXXXX>;
54 xen,uefi-mmap-desc-ver = <0xXXXXXXXX>;
/Documentation/arch/xtensa/
Dmmu.rst16 - RASID is 0x04030201 (reset state).
28 After step 2, we jump to virtual address in the range 0x40000000..0x5fffffff
29 or 0x00000000..0x1fffffff, depending on whether the kernel was loaded below
30 0x40000000 or above. That address corresponds to next instruction to execute
32 The scheme below assumes that the kernel is loaded below 0x40000000.
49 The default location of IO peripherals is above 0xf0000000. This may be changed
75 | Userspace | 0x00000000 TASK_SIZE
76 +------------------+ 0x40000000
78 | Page table | XCHAL_PAGE_TABLE_VADDR 0x80000000 XCHAL_PAGE_TABLE_SIZE
80 | KASAN shadow map | KASAN_SHADOW_START 0x80400000 KASAN_SHADOW_SIZE
[all …]