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/Documentation/devicetree/bindings/mfd/
Dbrcm,misc.yaml49 reg = <0xff802600 0xe4>;
53 ranges = <0x0 0x0 0xe4>;
57 reg = <0x44 0x4>;
/Documentation/devicetree/bindings/power/reset/
Dkeystone-reset.txt32 in format: <0>, <2>; It can be in random order and
33 begins from 0 to 3, as keystone can contain up to 4 SoC
42 reg = <0x02310000 0x200>;
47 reg = <0x02620000 0x1000>;
52 ti,syscon-pll = <&pllctrl 0xe4>;
53 ti,syscon-dev = <&devctrl 0x328>;
54 ti,wdt-list = <0>;
63 ti,syscon-pll = <&pllctrl 0xe4>;
64 ti,syscon-dev = <&devctrl 0x328>;
65 ti,wdt-list = <0>, <2>;
/Documentation/devicetree/bindings/arm/bcm/
Dbrcm,brcmstb.txt49 ranges = <0 0x00 0xf0000000 0x1000000>;
53 reg = <0x404000 0x51c>;
58 reg = <0x3e2400 0x5b4>;
64 reg = <0x452000 0x100>;
94 syscon-cpu = <&hif_cpubiuctrl 0x88 0x178>;
117 syscon = <&sun_top_ctrl 0x304 0x308>;
141 reg = <0x410000 0x400>;
170 "brcm,brcmstb-ddr-phy-v72.0"
182 - compatible : should contain "brcm,brcmstb-ddr-shimphy-v1.0"
199 memc@0 {
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/Documentation/devicetree/bindings/powerpc/fsl/
Dmsi-pic.txt45 reg = <0x41600 0x80>;
46 msi-available-ranges = <0 0x100>;
48 0xe0 0
49 0xe1 0
50 0xe2 0
51 0xe3 0
52 0xe4 0
53 0xe5 0
54 0xe6 0
55 0xe7 0>;
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/Documentation/devicetree/bindings/clock/
Dhisi-crg.txt39 reg = <0x12010000 0x10000>;
47 reg = <0x12110000 0x1000>;
49 resets = <&CRG 0xe4 0>;
/Documentation/devicetree/bindings/arm/hisilicon/
Dlow-pin-count.yaml21 pattern: '^isa@[0-9a-f]+$'
53 reg = <0xa01b0000 0x1000>;
58 reg = <0x01 0xe4 0x04>;
/Documentation/devicetree/bindings/nvmem/
Dst,stm32-romem.yaml34 "^.*@[0-9a-f]+$":
59 reg = <0x1fff7800 0x400>;
64 reg = <0x22c 0x2>;
68 reg = <0xe4 0x8>;
/Documentation/devicetree/bindings/media/
Damlogic,gx-vdec.yaml131 reg = <0xc8820000 0x10000>, <0xc110a580 0xe4>;
/Documentation/devicetree/bindings/phy/
Dphy-miphy28lp.txt56 reg = <0x9b22000 0xff>,
57 <0x9b09000 0xff>,
58 <0x9b04000 0xff>;
63 st,syscfg = <0x114 0x818 0xe0 0xec>;
71 reg = <0x9b2a000 0xff>,
72 <0x9b19000 0xff>,
73 <0x9b14000 0xff>;
78 st,syscfg = <0x118 0x81c 0xe4 0xf0>;
87 reg = <0x8f95000 0xff>,
88 <0x8f90000 0xff>;
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/Documentation/hwmon/
Dmlxreg-fan.rst21 pwm1 0xe3
22 fan1 (tacho1) 0xe4
23 fan2 (tacho2) 0xe5
24 fan3 (tacho3) 0xe6
25 fan4 (tacho4) 0xe7
26 fan5 (tacho5) 0xe8
27 fan6 (tacho6) 0xe9
28 fan7 (tacho7) 0xea
29 fan8 (tacho8) 0xeb
30 fan9 (tacho9) 0xec
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Dabituguru-datasheet.rst34 0xE0 and 0xE4, so we don't have to scan any port-range, just check what the two
35 ports are holding for detection. We will refer to 0xE0 as CMD (command-port)
36 and 0xE4 as DATA because Abit refers to them with these names.
38 If DATA holds 0x00 or 0x08 and CMD holds 0x00 or 0xAC an uGuru could be
40 after a reboot uGuru will hold 0x00 here, but if the driver is removed and
41 later on attached again data-port will hold 0x08, more about this later.
44 turned up which will hold 0x00 instead of 0xAC at the CMD port, thus we also
46 hold 0x09 and will only hold 0x08 after reading CMD first, so CMD must be read
72 bank 0x24 for example the addressing within the bank selects a PWM output not
87 To put the uGuru in ready mode first write 0x00 to DATA and then wait for DATA
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Dpc87360.rst27 - 0: None
56 PC87360 - 2 2 - 0xE1
57 PC87363 - 2 2 - 0xE8
58 PC87364 - 3 3 - 0xE4
59 PC87365 11 3 3 2 0xE5
60 PC87366 11 3 3 3-4 0xE9
64 standard Super I/O addresses is used (0x2E/0x2F or 0x4E/0x4F)
111 PWM (pulse width modulation) values range from 0 to 255, with 0 meaning
/Documentation/filesystems/ext4/
Dsuper.rst12 number is either 0 or a power of 3, 5, or 7. If the flag is not set,
29 * - 0x0
33 * - 0x4
37 * - 0x8
41 * - 0xC
45 * - 0x10
49 * - 0x14
53 is typically 0 for all other block sizes.
54 * - 0x18
58 * - 0x1C
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/Documentation/admin-guide/media/
Dvivid.rst63 hexadecimal values, one for each instance. The default is 0xe1d3d.
66 - bit 0: Video Capture node
67 - bit 2-3: VBI Capture node: 0 = none, 1 = raw vbi, 2 = sliced vbi, 3 = both
71 - bit 10-11: VBI Output node: 0 = none, 1 = raw vbi, 2 = sliced vbi, 3 = both
84 n_devs=4 node_types=0x1,0x1,0x100,0x100
94 the input types for each instance, the default is 0xe4. This defines
97 pair gives the type and bits 0-1 map to input 0, bits 2-3 map to input 1,
105 So to create a video capture device with 8 inputs where input 0 is a TV
111 num_inputs=8 input_types=0xffa9
121 the output types for each instance, the default is 0x02. This defines
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/Documentation/arch/x86/
Dboot.rst28 Protocol 2.02 (Kernel 2.4.0-test3-pre3) New command line protocol.
99 0A0000 +------------------------+
121 0x100000 ("high memory"), and the kernel real-mode block (boot sector,
123 0x10000 and end of low memory. Unfortunately, in protocols 2.00 and
124 2.01 the 0x90000+ memory range is still used internally by the kernel;
139 0x90000 segment, the boot loader should make sure not to use memory
140 above the 0x9A000 point; too many BIOSes will break above that point.
149 0A0000 +------------------------+
180 following header at offset 0x01f1. The real-mode code can total up to
195 01FE/2 ALL boot_flag 0xAA55 magic number
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/Documentation/driver-api/media/drivers/
Dcx2341x-devel.rst23 ivtvctl -O min=0x02000000,max=0x020000ff
32 (Base Address Register 0). The addresses here are offsets relative to the
37 0x00000000-0x00ffffff Encoder memory space
38 0x00000000-0x0003ffff Encode.rom
44 0x01000000-0x01ffffff Decoder memory space
45 0x01000000-0x0103ffff Decode.rom
47 0x0114b000-0x0115afff Audio.rom (deprecated?)
49 0x02000000-0x0200ffff Register Space
54 The registers occupy the 64k space starting at the 0x02000000 offset from BAR0.
59 DMA Registers 0x000-0xff:
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