Searched +full:0 +full:xe8000000 (Results 1 – 4 of 4) sorted by relevance
| /Documentation/devicetree/bindings/pci/ |
| D | aardvark-pci.txt | 39 reg = <0 0xd0070000 0 0x20000>;
42 bus-range = <0x00 0xff>;
47 ranges = <0x82000000 0 0xe8000000 0 0xe8000000 0 0x1000000 /* Port 0 MEM */
48 0x81000000 0 0xe9000000 0 0xe9000000 0 0x10000>; /* Port 0 IO*/
49 interrupt-map-mask = <0 0 0 7>;
50 interrupt-map = <0 0 0 1 &pcie_intc 0>,
51 <0 0 0 2 &pcie_intc 1>,
52 <0 0 0 3 &pcie_intc 2>,
53 <0 0 0 4 &pcie_intc 3>;
54 phys = <&comphy1 0>;
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| D | nvidia,tegra194-pcie.yaml | 85 - const: p2u-0
123 0: C0
132 0 : C0
260 bus@0 {
263 ranges = <0x0 0x0 0x0 0x8 0x0>;
268 reg = <0x0 0x14180000 0x0 0x00020000>, /* appl registers (128K) */
269 <0x0 0x38000000 0x0 0x00040000>, /* configuration space (256K) */
270 <0x0 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
271 <0x0 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */
278 linux,pci-domain = <0>;
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| /Documentation/devicetree/bindings/bus/ |
| D | mvebu-mbus.txt | 65 pcie-mem-aperture = <0xe0000000 0x8000000>;
66 pcie-io-aperture = <0xe8000000 0x100000>;
73 reg = <0x20000 0x100>, <0x20180 0x20>, <0x20250 0x8>;
87 0xSIAA0000 0x00oooooo
91 S = 0x0 for a MBus valid window
92 S = 0xf for a non-valid window (see below)
94 If S = 0x0, then:
99 If S = 0xf, then:
105 (S = 0x0), an address decoding window is allocated. On the other side,
106 entries for translation that do not correspond to valid windows (S = 0xf)
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| /Documentation/devicetree/bindings/memory-controllers/ |
| D | nvidia,tegra30-emc.yaml | 35 const: 0
53 "^emc-timings-[0-9]+$":
62 "^timing-[0-9]+$":
75 minimum: 0
91 Mode Register 0.
98 minimum: 0
239 reg = <0x7000f400 0x400>;
240 interrupts = <0 78 4>;
247 #interconnect-cells = <0>;
255 nvidia,emc-auto-cal-interval = <0x001fffff>;
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