| /Documentation/devicetree/bindings/mmc/ |
| D | sdhci-am654.yaml | 64 minimum: 0
65 maximum: 0xf
70 minimum: 0
71 maximum: 0xf
76 minimum: 0
77 maximum: 0xf
82 minimum: 0
83 maximum: 0xf
88 minimum: 0
89 maximum: 0xf
[all …]
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| D | marvell,xenon-sdhci.yaml | 66 minimum: 0
70 Operation Control Register Bit[7:0]. Set/clear the corresponding bit to
91 minimum: 0
92 maximum: 0x1f
93 default: 0xf
100 minimum: 0
101 maximum: 0x1f
102 default: 0xf
111 default: 0x4
133 default: 0x9
[all …]
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| /Documentation/devicetree/bindings/pci/ |
| D | pci-msi.txt | 13 * Bits [2:0] are the Function number.
67 reg = <0xa 0x1>;
74 reg = <0xf 0x1>;
82 msi-map = <0x0 &msi_a 0x0 0x10000>,
95 reg = <0xa 0x1>;
102 reg = <0xf 0x1>;
110 msi-map = <0x0 &msi_a 0x0 0x100>,
111 msi-map-mask = <0xff>
124 reg = <0xa 0x1>;
131 reg = <0xf 0x1>;
[all …]
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| D | pci-iommu.txt | 13 * Bits [2:0] are the Function number.
56 reg = <0xa 0x1>;
62 reg = <0xf 0x1>;
70 iommu-map = <0x0 &iommu 0x0 0x10000>;
83 reg = <0xa 0x1>;
89 reg = <0xf 0x1>;
97 iommu-map = <0x0 &iommu 0x0 0x10000>;
98 iommu-map-mask = <0xfff8>;
111 reg = <0xa 0x1>;
117 reg = <0xf 0x1>;
[all …]
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| /Documentation/arch/arm/ |
| D | vlocks.rst | 33 int currently_voting[NR_CPUS] = { 0, };
42 currently_voting[this_cpu] = 0;
48 currently_voting[this_cpu] = 0;
52 while (currently_voting[i] != 0)
100 my_town = towns[(this_cpu >> 4) & 0xf];
101 I_won = vlock_trylock(my_town, this_cpu & 0xf);
104 my_state = states[(this_cpu >> 8) & 0xf];
105 I_won = vlock_lock(my_state, this_cpu & 0xf));
108 I_won = vlock_lock(the_whole_country, this_cpu & 0xf];
134 CMP Rt, #0
[all …]
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| /Documentation/devicetree/bindings/mfd/ |
| D | rohm,bd9571mwv.yaml | 36 minimum: 0x0
37 maximum: 0xf
39 Value to use for DDR-Backup Power (default 0).
42 - bit 0: DDR0
103 #size-cells = <0>;
107 reg = <0x30>;
109 interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
114 rohm,ddr-backup-power = <0xf>;
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | fsl,ls-extirq.yaml | 38 const: 0
76 - const: 0x7
77 - const: 0
92 - const: 0xf
93 - const: 0
115 - const: 0xf
116 - const: 0
126 #address-cells = <0>;
128 reg = <0x1ac 4>;
130 <0 0 &gic GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
[all …]
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| /Documentation/devicetree/bindings/net/ieee802154/ |
| D | at86rf230.txt | 16 arrays of xtal pins: 0 = +0 pF, 0xf = +4.5 pF
20 at86rf231@0 {
23 reg = <0>;
26 xtal-trim = /bits/ 8 <0x06>;
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| /Documentation/devicetree/bindings/iio/accel/ |
| D | kionix,kxcjk1013.yaml | 44 #size-cells = <0>;
48 reg = <0xf>;
49 mount-matrix = "0", "1", "0",
50 "1", "0", "0",
51 "0", "0", "1";
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| /Documentation/devicetree/bindings/soc/bcm/ |
| D | brcm,bcm2835-vchiq.yaml | 49 reg = <0x7e00b840 0xf>;
50 interrupts = <0 2>;
|
| /Documentation/devicetree/bindings/cpufreq/ |
| D | imx-cpufreq-dt.txt | 15 0: Consumer
27 /* grade >= 0, consumer only */
28 opp-supported-hw = <0xf>, <0x3>;
35 opp-supported-hw = <0xe>, <0x7>;
|
| /Documentation/devicetree/bindings/phy/ |
| D | rockchip,rk3399-emmc-phy.yaml | 42 default: 0x4
43 maximum: 0xf
46 const: 0
59 reg = <0xf780 0x20>;
63 #phy-cells = <0>;
|
| D | apm-xgene-phy.txt | 10 the mode of the PHY. Possible values are 0 (SATA),
20 supported link speed on the host. Range from 0 to
22 - apm,tx-eye-direction : Eye tuning manual control direction. 0 means sample
26 supported link speed on the host. Default is 0.
30 between 0 to 31 in unit of dB. Default is 3.
33 Range is between 0 to 199500 in unit of uV.
37 speed on the host. Range is 0 to 273000 in unit of
38 uV. Default is 0.
41 speed on the host. Range is 0 to 127400 in unit uV.
42 Default is 0x0.
[all …]
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| /Documentation/devicetree/bindings/spmi/ |
| D | spmi.yaml | 31 const: 0
34 "@[0-9a-f]$":
43 - minimum: 0
44 maximum: 0xf
45 - enum: [ 0 ]
47 0 means user ID address. 1 is reserved for group ID
62 spmi@0 {
63 reg = <0 0>;
66 #size-cells = <0>;
68 child@0 {
[all …]
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| /Documentation/devicetree/bindings/clock/ |
| D | xgene.txt | 50 Default is 0.
51 - csr-mask : CSR reset mask bit. Default is 0xF.
53 Default is 0x8.
54 - enable-mask : CSR enable mask bit. Default is 0xF.
56 Default is 0x0.
57 - divider-width : Width of the divider register. Default is 0.
58 - divider-shift : Bit shift of the divider register. Default is 0.
65 clocks = <&refclk 0>;
67 reg = <0x0 0x17000100 0x0 0x1000>;
69 type = <0>;
[all …]
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| /Documentation/admin-guide/perf/ |
| D | hns3-pmu.rst | 44 config=0x00204
46 config=0x10204
51 The bits 0~15 of config (here 0x0204) are the true hardware event code. If
52 two events have same value of bits 0~15 of config, that means they are
53 event pair. And the bit 16 of config indicates getting counter 0 or
59 counter 0 / counter 1
75 …$# perf stat -g -e hns3_pmu_sicl_0/config=0x00002,global=1/ -e hns3_pmu_sicl_0/config=0x10002,glob…
86 $# perf stat -a -e hns3_pmu_sicl_0/config=0x1020F,global=1/ -I 1000
90 is same as mac id. The "tc" filter option must be set to 0xF in this mode,
95 $# perf stat -a -e hns3_pmu_sicl_0/config=0x1020F,port=0,tc=0xF/ -I 1000
[all …]
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| /Documentation/devicetree/bindings/sound/ |
| D | cs35l33.txt | 22 0, then VBST = VP. If greater than 0, the boost voltage will be 3300mV with
31 20ms. If this property is set to 0,1,2,3 then ramp times would be 40ms,
39 ADC data word. This property can be set as a value of 0 for bits 15 down
40 to 0, 6 for 21 down to 6, 7, for 22 down to 7, 8 for 23 down to 8.
54 LRCLK cycles. If this property is set to 0, 1, 2, or 3 then the memory
64 0xF).
72 from 0 to 7 for delays of 5ms, 10ms, 50ms, 100ms, 200ms, 500ms, 1000ms.
80 The reference voltage starts at 3000mV with a value of 0x3 and is increased
85 tracking. This property can be set to values from 0 to 3 with rates of 128
90 using VPMON. This property can be set to values from 0 to 6 starting at
[all …]
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| /Documentation/devicetree/bindings/bus/ |
| D | mvebu-mbus.txt | 65 pcie-mem-aperture = <0xe0000000 0x8000000>;
66 pcie-io-aperture = <0xe8000000 0x100000>;
73 reg = <0x20000 0x100>, <0x20180 0x20>, <0x20250 0x8>;
87 0xSIAA0000 0x00oooooo
91 S = 0x0 for a MBus valid window
92 S = 0xf for a non-valid window (see below)
94 If S = 0x0, then:
99 If S = 0xf, then:
105 (S = 0x0), an address decoding window is allocated. On the other side,
106 entries for translation that do not correspond to valid windows (S = 0xf)
[all …]
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| /Documentation/driver-api/ |
| D | connector.rst | 53 __u8 data[0];
121 l_local.nl_pid = 0;
136 option with the NETLINK_DROP_MEMBERSHIP parameter which is defined as 0.
140 In case of connector it is CN_NETLINK_USERS + 0xf, so if you want to use
142 Additional 0xf numbers are allocated to be used by non-in-kernel users.
144 Due to this limitation, group 0xffffffff does not work now, so one can
|
| /Documentation/devicetree/bindings/iio/adc/ |
| D | ti,am3359-adc.yaml | 27 description: List of analog inputs available for ADC. AIN0 = 0, AIN1 = 1 and
37 the start of ADC conversion. Maximum value is 0x3FFFF.
45 to sample (to hold start of conversion high). Maximum value is 0xFF.
72 ti,chan-step-opendelay = <0x098 0x3ffff 0x098 0x0>;
73 ti,chan-step-sampledelay = <0xff 0x0 0xf 0x0>;
|
| /Documentation/devicetree/bindings/usb/ |
| D | chipidea,usb2-imx.yaml | 103 pins after a J-to-K or K-to-J transition. The range is from 0x0 to
104 0x3, the default value is 0x1. Details can refer to TXPREEMPAMPTUNE0
107 minimum: 0x0
108 maximum: 0x3
113 level voltage. The range is from 0x0 to 0xf, the default value is
114 0x3. Details can refer to TXVREFTUNE0 bits of USBNC_n_PHY_CFG1.
116 minimum: 0x0
117 maximum: 0xf
124 to design default time. (0:-10%; 1:design default; 2:+15%; 3:+20%)
127 minimum: 0
[all …]
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| /Documentation/fault-injection/ |
| D | nvme-fault-injection.rst | 33 name fault_inject, interval 1, probability 100, space 0, times 1
34 CPU: 0 PID: 0 Comm: swapper/0 Not tainted 4.15.0-rc8+ #2
39 dump_stack+0x5c/0x7d
40 should_fail+0x148/0x170
41 nvme_should_fail+0x2f/0x50 [nvme_core]
42 nvme_process_cq+0xe7/0x1d0 [nvme]
43 nvme_irq+0x1e/0x40 [nvme]
44 __handle_irq_event_percpu+0x3a/0x190
45 handle_irq_event_percpu+0x30/0x70
46 handle_irq_event+0x36/0x60
[all …]
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| /Documentation/trace/coresight/ |
| D | ultrasoc-smb.rst | 38 BIT(0) is zero value which means the buffer is empty.
58 ReadWrite, 0x0, 0x95100000, 0x951FFFFF, 0x0, 0x100000) \
60 ReadWrite, 0x0, 0x50000000, 0x53FFFFFF, 0x0, 0x4000000) \
66 0, \
72 Package() {0x8, 0, \_SB.S00.SL11.CL28.F008, 0}, \
73 Package() {0x9, 0, \_SB.S00.SL11.CL29.F009, 0}, \
74 Package() {0xa, 0, \_SB.S00.SL11.CL2A.F010, 0}, \
75 Package() {0xb, 0, \_SB.S00.SL11.CL2B.F011, 0}, \
76 Package() {0xc, 0, \_SB.S00.SL11.CL2C.F012, 0}, \
77 Package() {0xd, 0, \_SB.S00.SL11.CL2D.F013, 0}, \
[all …]
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| /Documentation/devicetree/bindings/powerpc/fsl/ |
| D | srio.txt | 9 Revision Register (SRIO IPBRR1) Major ID equal to 0x01c0.
20 be set to 0x11000.
83 reg = <0xf 0xfe0c0000 0 0x11000>;
94 ranges = <0 0 0xc 0x20000000 0 0x10000000>;
102 ranges = <0 0 0xc 0x30000000 0 0x10000000>;
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| /Documentation/arch/arm/samsung/ |
| D | clksrc-change-registers.awk | 26 p[0] = tp[2]
32 if (0)
35 if (f ~ /0x1/)
37 else if (f ~ /0x3/)
39 else if (f ~ /0x7/)
41 else if (f ~ /0xf/)
51 if (id <= 0) {
69 while (getline line < ARGV[1] > 0) {
73 name = fields[0]
74 if (0)
[all …]
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