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Searched +full:0 +full:xf0000000 (Results 1 – 11 of 11) sorted by relevance

/Documentation/devicetree/bindings/bus/
Dmicrosoft,vmbus.yaml51 ranges = <0x0f 0xf0000000 0x0f 0xf0000000 0x10000000>;
Dmvebu-mbus.txt65 pcie-mem-aperture = <0xe0000000 0x8000000>;
66 pcie-io-aperture = <0xe8000000 0x100000>;
73 reg = <0x20000 0x100>, <0x20180 0x20>, <0x20250 0x8>;
87 0xSIAA0000 0x00oooooo
91 S = 0x0 for a MBus valid window
92 S = 0xf for a non-valid window (see below)
94 If S = 0x0, then:
99 If S = 0xf, then:
105 (S = 0x0), an address decoding window is allocated. On the other side,
106 entries for translation that do not correspond to valid windows (S = 0xf)
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/Documentation/devicetree/bindings/timer/
Dst,spear-timer.txt14 reg = <0xf0000000 0x400>;
Darm,arch_timer_mmio.yaml63 '^frame@[0-9a-f]+$':
70 minimum: 0
104 ranges = <0 0xf0001000 0x1000>;
105 reg = <0xf0000000 0x1000>;
108 frame@0 {
109 frame-number = <0>;
110 interrupts = <0 13 0x8>,
111 <0 14 0x8>;
112 reg = <0x0000 0x1000>,
113 <0x1000 0x1000>;
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/Documentation/devicetree/bindings/memory-controllers/
Dsamsung,s5pv210-dmc.yaml32 reg = <0xf0000000 0x1000>;
Dmvebu-devbus.txt24 0 <physical address of mapping> <size>
46 - devbus,badr-skew-ps: Defines the time delay from from A[2:0] toggle,
53 ALE[0] to the cycle that the first read data is sampled
63 DEV_OEn assertion. If set to 0 (default),
72 de-assertion of DEV_CSn. If set to 0 (default),
85 - devbus,ale-wr-ps: Defines the time delay from the ALE[0] negation cycle
90 A[2:0] and Data are kept valid as long as DEV_WEn
97 DEV_A[2:0] and Data are kept valid (do not toggle) for
105 0: False
115 will start at base address 0xf0000000, with a size 0x1000000 (16 MiB)
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/Documentation/devicetree/bindings/soc/litex/
Dlitex,soc-controller.yaml37 reg = <0xf0000000 0xc>;
/Documentation/arch/xtensa/
Dmmu.rst16 - RASID is 0x04030201 (reset state).
28 After step 2, we jump to virtual address in the range 0x40000000..0x5fffffff
29 or 0x00000000..0x1fffffff, depending on whether the kernel was loaded below
30 0x40000000 or above. That address corresponds to next instruction to execute
32 The scheme below assumes that the kernel is loaded below 0x40000000.
49 The default location of IO peripherals is above 0xf0000000. This may be changed
75 | Userspace | 0x00000000 TASK_SIZE
76 +------------------+ 0x40000000
78 | Page table | XCHAL_PAGE_TABLE_VADDR 0x80000000 XCHAL_PAGE_TABLE_SIZE
80 | KASAN shadow map | KASAN_SHADOW_START 0x80400000 KASAN_SHADOW_SIZE
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/Documentation/devicetree/bindings/pci/
Dhisilicon-histb-pcie.txt38 - phys: List of phandle and phy mode specifier, should be 0.
44 reg = <0xf9860000 0x1000>,
45 <0xf0000000 0x2000>,
46 <0xf2000000 0x01000000>;
51 bus-range = <0 15>;
53 ranges=<0x81000000 0 0 0xf4000000 0 0x00010000
54 0x82000000 0 0xf3000000 0xf3000000 0 0x01000000>;
58 interrupt-map-mask = <0 0 0 0>;
59 interrupt-map = <0 0 0 0 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
65 resets = <&crg 0x18c 6>, <&crg 0x18c 5>, <&crg 0x18c 4>;
Dsifive,fu740-pcie.yaml94 reg = <0xe 0x00000000 0x0 0x80000000>,
95 <0xd 0xf0000000 0x0 0x10000000>,
96 <0x0 0x100d0000 0x0 0x1000>;
100 bus-range = <0x0 0xff>;
101 ranges = <0x81000000 0x0 0x60080000 0x0 0x60080000 0x0 0x10000>, /* I/O */
102 <0x82000000 0x0 0x60090000 0x0 0x60090000 0x0 0xff70000>, /* mem */
103 <0x82000000 0x0 0x70000000 0x0 0x70000000 0x0 0x1000000>, /* mem */
104 … <0xc3000000 0x20 0x00000000 0x20 0x00000000 0x20 0x00000000>; /* mem prefetchable */
105 num-lanes = <0x8>;
109 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
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/Documentation/devicetree/bindings/arm/bcm/
Dbrcm,brcmstb.txt49 ranges = <0 0x00 0xf0000000 0x1000000>;
53 reg = <0x404000 0x51c>;
58 reg = <0x3e2400 0x5b4>;
64 reg = <0x452000 0x100>;
94 syscon-cpu = <&hif_cpubiuctrl 0x88 0x178>;
117 syscon = <&sun_top_ctrl 0x304 0x308>;
141 reg = <0x410000 0x400>;
170 "brcm,brcmstb-ddr-phy-v72.0"
182 - compatible : should contain "brcm,brcmstb-ddr-shimphy-v1.0"
199 memc@0 {
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