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/Documentation/devicetree/bindings/spi/
Dnuvoton,npcm-fiu.txt17 - #size-cells : should be 0.
25 - pinctrl-0 : phandle referencing pin configuration of the device.
34 fiu0 represent fiu 0 controller
39 fiu0 represent fiu 0 controller
48 #size-cells = <0>;
49 reg = <0xfb000000 0x1000>, <0x80000000 0x10000000>;
53 pinctrl-0 = <&spi3_pins>;
54 flash@0 {
/Documentation/arch/x86/
Dmtrr.rst73 reg00: base=0x00000000 ( 0MB), size= 128MB: write-back, count=1
74 reg01: base=0x08000000 ( 128MB), size= 64MB: write-back, count=1
78 # echo "base=0xf8000000 size=0x400000 type=write-combining" >! /proc/mtrr
82 # echo "base=0xf8000000 size=0x400000 type=write-combining" >| /proc/mtrr
87 reg00: base=0x00000000 ( 0MB), size= 128MB: write-back, count=1
88 reg01: base=0x08000000 ( 128MB), size= 64MB: write-back, count=1
89 reg02: base=0xf8000000 (3968MB), size= 4MB: write-combining, count=1
91 This is for video RAM at base address 0xf8000000 and size 4 megabytes. To
96 (--) S3: PCI: 968 rev 0, Linear FB @ 0xf8000000
107 That's 4 megabytes, which is 0x400000 bytes (in hexadecimal).
[all …]
/Documentation/devicetree/bindings/pci/
Dcdns,cdns-pcie-host.yaml44 bus-range = <0x0 0xff>;
45 linux,pci-domain = <0>;
46 vendor-id = <0x17cd>;
47 device-id = <0x0200>;
49 reg = <0x0 0xfb000000 0x0 0x01000000>,
50 <0x0 0x41000000 0x0 0x00001000>;
53 ranges = <0x02000000 0x0 0x42000000 0x0 0x42000000 0x0 0x1000000>,
54 <0x01000000 0x0 0x43000000 0x0 0x43000000 0x0 0x0010000>;
55 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x1 0x00000000>;
57 #interrupt-cells = <0x1>;
[all …]
/Documentation/devicetree/bindings/display/bridge/
Dcdns,mhdp8546.yaml64 port@0:
90 - port@0
137 reg = <0xf0 0xfb000000 0x0 0x1000000>;
146 #size-cells = <0>;
148 port@0 {
149 reg = <0>;
/Documentation/devicetree/bindings/gpu/
Darm,mali-valhall-csf.yaml121 reg = <0xfb000000 0x200000>;
122 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH 0>,
123 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH 0>,
124 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH 0>;