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/Documentation/devicetree/bindings/pci/
Drcar-gen4-pci-host.yaml98 reg = <0 0xe65d0000 0 0x1000>, <0 0xe65d2000 0 0x0800>,
99 <0 0xe65d3000 0 0x2000>, <0 0xe65d5000 0 0x1200>,
100 <0 0xe65d6200 0 0x0e00>, <0 0xe65d7000 0 0x0400>,
101 <0 0xfe000000 0 0x400000>;
117 bus-range = <0x00 0xff>;
119 ranges = <0x01000000 0 0x00000000 0 0xfe000000 0 0x00400000>,
120 <0x02000000 0 0x30000000 0 0x30000000 0 0x10000000>;
121 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
123 interrupt-map-mask = <0 0 0 7>;
124 interrupt-map = <0 0 0 1 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
[all …]
Drcar-pci-ep.yaml79 reg = <0xfe000000 0x80000>,
80 <0xfe100000 0x100000>,
81 <0xfe200000 0x200000>,
82 <0x30000000 0x8000000>,
83 <0x38000000 0x8000000>;
Drcar-gen4-pci-ep.yaml100 reg = <0 0xe65d0000 0 0x2000>, <0 0xe65d2000 0 0x1000>,
101 <0 0xe65d3000 0 0x2000>, <0 0xe65d5000 0 0x1200>,
102 <0 0xe65d6200 0 0x0e00>, <0 0xe65d7000 0 0x0400>,
103 <0 0xfe000000 0 0x400000>;
Drcar-pci-host.yaml115 reg = <0 0xfe000000 0 0x80000>;
118 bus-range = <0x00 0xff>;
120 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
121 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
122 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
123 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
124 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>,
125 <0x42000000 2 0x00000000 2 0x00000000 0 0x40000000>;
130 interrupt-map-mask = <0 0 0 0>;
131 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
/Documentation/devicetree/bindings/powerpc/fsl/
Dlbc.txt19 reg = <0xf0010100 0x40>;
21 ranges = <0x0 0x0 0xfe000000 0x02000000
22 0x1 0x0 0xf4500000 0x00008000
23 0x2 0x0 0xfd810000 0x00010000>;
25 flash@0,0 {
27 reg = <0x0 0x0 0x2000000>;
32 board-control@1,0 {
33 reg = <0x1 0x0 0x20>;
37 simple-periph@2,0 {
39 reg = <0x2 0x0 0x10000>;
[all …]
/Documentation/devicetree/bindings/clock/
Damlogic,s4-peripherals-clkc.yaml76 reg = <0xfe000000 0x49c>;
/Documentation/devicetree/bindings/display/
Dst,stih4xx.txt97 - pinctrl-0: pin control handle
124 reg = <0xfe85A800 0x300>;
130 reg = <0xfd348000 0x400>;
136 reg = <0xfe858200 0x300>;
142 reg = <0xfd348400 0x400>;
149 reg = <0xfee82800 0x200>;
156 reg = <0xfee82a00 0x200>;
163 reg = <0xfd349000 0x200>, <0xfd320000 0x10000>;
170 reg = <0xfd349200 0x200>, <0xfd320000 0x10000>;
181 reg = <0xfd340000 0x1000>;
[all …]