Searched +full:1 +full:- +full:wire (Results 1 – 25 of 141) sorted by relevance
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| /Documentation/w1/masters/ |
| D | w1-uart.rst | 1 .. SPDX-License-Identifier: GPL-2.0-or-later 4 Kernel driver w1-uart 11 ----------- 13 UART 1-Wire bus driver. The driver utilizes the UART interface via the 14 Serial Device Bus to create the 1-Wire timing patterns as described in 15 the document `"Using a UART to Implement a 1-Wire Bus Master"`_. 17 …ng a UART to Implement a 1-Wire Bus Master": https://www.analog.com/en/technical-articles/using-a-… 19 In short, the UART peripheral must support full-duplex and operate in 20 open-drain mode. The timing patterns are generated by a specific 21 combination of baud-rate and transmitted byte, which corresponds to a [all …]
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| D | omap-hdq.rst | 2 Kernel driver for omap HDQ/1-wire module 7 HDQ/1-wire controller on the TI OMAP 2430/3430 platforms. 15 The HDQ/1-Wire module of TI OMAP2430/3430 platforms implement the hardware 17 Semiconductor 1-Wire protocols. These protocols use a single wire for 18 communication between the master (HDQ/1-Wire controller) and the slave 19 (HDQ/1-Wire external compliant device). 21 A typical application of the HDQ/1-Wire module is the communication with battery 24 The controller supports operation in both HDQ and 1-wire mode. The essential 25 difference between the HDQ and 1-wire mode is how the slave device responds to 29 does not respond with a presence pulse as it does in the 1-Wire protocol. [all …]
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| D | w1-gpio.rst | 2 Kernel driver w1-gpio 9 ----------- 11 GPIO 1-wire bus master driver. The driver uses the GPIO API to control the 12 wire and the GPIO pin can be specified using GPIO machine descriptor tables. 14 Documentation/devicetree/bindings/w1/w1-gpio.yaml 17 Example (mach-at91) 18 ------------------- 23 #include <linux/w1-gpio.h> 26 .dev_id = "w1-gpio", 28 GPIO_LOOKUP_IDX("at91-gpio", AT91_PIN_PB20, NULL, 0, [all …]
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| /Documentation/devicetree/bindings/w1/ |
| D | w1-uart.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/w1/w1-uart.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: UART 1-Wire Bus 10 - Christoph Winklhofer <cj.winklhofer@gmail.com> 13 UART 1-wire bus. Utilizes the UART interface via the Serial Device Bus 14 to create the 1-Wire timing patterns. 16 The UART peripheral must support full-duplex and operate in open-drain 18 baud-rate and transmitted byte, which corresponds to a 1-Wire read bit, [all …]
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| D | amd,axi-1wire-host.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/w1/amd,axi-1wire-host.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: AMD AXI 1-wire bus host for programmable logic 10 - Kris Chaplin <kris.chaplin@amd.com> 14 const: amd,axi-1wire-host 17 maxItems: 1 20 maxItems: 1 23 maxItems: 1 [all …]
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| D | omap-hdq.txt | 1 * OMAP HDQ One wire bus master controller 4 - compatible : should be "ti,omap3-1w" or "ti,am4372-hdq" 5 - reg : Address and length of the register set for the device 6 - interrupts : interrupt line. 7 - ti,hwmods : "hdq1w" 10 - ti,mode: should be "hdq": HDQ mode "1w": one-wire mode. 15 - From omap3.dtsi 16 hdqw1w: 1w@480b2000 { 17 compatible = "ti,omap3-1w";
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| D | maxim,ds2482.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Maxim One wire bus master controller 10 - Stefan Wahren <stefan.wahren@chargebyte.com> 13 I2C to 1-wire bridges 15 https://www.analog.com/media/en/technical-documentation/data-sheets/ds2482-100.pdf 16 https://www.analog.com/media/en/technical-documentation/data-sheets/DS2482-800.pdf 17 https://www.analog.com/media/en/technical-documentation/data-sheets/DS2484.pdf 22 - maxim,ds2482 [all …]
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| /Documentation/devicetree/bindings/iio/temperature/ |
| D | maxim,max31865.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Navin Sankar Velliangiri <navin@linumiz.com> 20 maxItems: 1 22 maxim,3-wire: 25 enables 3-wire RTD connection. Else 2-wire or 4-wire RTD connection. 28 spi-cpha: true 31 - compatible 32 - reg [all …]
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| /Documentation/peci/ |
| D | peci.rst | 1 .. SPDX-License-Identifier: GPL-2.0-only 13 controller is acting as a PECI originator and the processor - as 15 PECI can be used in both single processor and multiple-processor based 24 PECI Wire 25 --------- 27 PECI Wire interface uses a single wire for self-clocking and data 28 transfer. It does not require any additional control lines - the 29 physical layer is a self-clocked one-wire bus signal that begins each 32 value is logic '0' or logic '1'. PECI Wire also includes variable data 35 For PECI Wire, each processor package will utilize unique, fixed [all …]
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | intel,ce4100-lapic.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/interrupt-controller/intel,ce4100-lapic.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Rahul Tanwar <rtanwar@maxlinear.com> 20 See [1] Chapter 8 for more details. 28 [1] https://pdos.csail.mit.edu/6.828/2008/readings/ia32/IA32-3A.pdf 32 const: intel,ce4100-lapic 35 maxItems: 1 37 interrupt-controller: true [all …]
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| /Documentation/devicetree/bindings/display/panel/ |
| D | tpo,tpg110.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Linus Walleij <linus.walleij@linaro.org> 11 - Thierry Reding <thierry.reding@gmail.com> 17 and other properties, and has a control interface over 3WIRE 20 self-describing. 22 +--------+ 23 SPI -> | TPO | -> physical display 24 RGB -> | TPG110 | [all …]
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| D | leadtek,ltk035c5444t.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Leadtek ltk035c5444t 3.5" (640x480 pixels) 24-bit IPS LCD panel 10 - Paul Cercueil <paul@crapouillou.net> 11 - Christophe Branchereau <cbranchereau@gmail.com> 14 - $ref: panel-common.yaml# 15 - $ref: /schemas/spi/spi-peripheral-props.yaml# 22 maxItems: 1 24 spi-3wire: true [all …]
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| D | kingdisplay,kd035g6-54nt.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/display/panel/kingdisplay,kd035g6-54nt.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: King Display KD035G6-54NT 3.5" (320x240 pixels) 24-bit TFT LCD panel 10 - Paul Cercueil <paul@crapouillou.net> 13 - $ref: panel-common.yaml# 14 - $ref: /schemas/spi/spi-peripheral-props.yaml# 18 const: kingdisplay,kd035g6-54nt 21 maxItems: 1 [all …]
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| D | fascontek,fs035vg158.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Fascontek FS035VG158 3.5" (640x480 pixels) 24-bit IPS LCD panel 10 - John Watts <contact@jookia.org> 13 - $ref: panel-common.yaml# 14 - $ref: /schemas/spi/spi-peripheral-props.yaml# 21 maxItems: 1 23 spi-3wire: true 26 - compatible [all …]
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| D | anbernic,rg35xx-plus-panel.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/display/panel/anbernic,rg35xx-plus-panel.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Anbernic RG35XX series (WL-355608-A8) 3.5" 640x480 24-bit IPS LCD panel 10 - Ryan Walklin <ryan@testtoast.com> 13 - $ref: panel-common.yaml# 14 - $ref: /schemas/spi/spi-peripheral-props.yaml# 19 - const: anbernic,rg35xx-plus-panel 20 - items: [all …]
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| /Documentation/devicetree/bindings/spi/ |
| D | icpdas-lp8841-spi-rtc.txt | 1 * ICP DAS LP-8841 SPI Controller for RTC 3 ICP DAS LP-8841 contains a DS-1302 RTC. RTC is connected to an IO 6 The device uses the standard MicroWire half-duplex transfer timing. 13 - #address-cells: should be 1 15 - #size-cells: should be 0 17 - compatible: should be "icpdas,lp8841-spi-rtc" 19 - reg: should provide IO memory address 23 - There can be only one slave device. 25 - The spi slave node should claim the following flags which are 28 - spi-3wire: The master itself has only 3 wire. It cannor work in [all …]
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| /Documentation/devicetree/bindings/sound/ |
| D | awinic,aw8738.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Stephan Gerhold <stephan@gerhold.net> 14 (set using one-wire pulse control). The mode configures the speaker-guard 18 - $ref: dai-common.yaml# 24 mode-gpios: 26 GPIO used for one-wire pulse control. The pin is typically called SHDN 27 (active-low), but this is misleading since it is actually more than 29 maxItems: 1 [all …]
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| D | mt6359.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Eason Yen <eason.yen@mediatek.com> 11 - Jiaxin Yu <jiaxin.yu@mediatek.com> 12 - Shane Chien <shane.chien@mediatek.com> 20 mediatek,dmic-mode: 24 signal. 0 means two wires, 1 means one wire. Default value is 0. 26 - 0 # two wires 27 - 1 # one wire [all …]
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| /Documentation/devicetree/bindings/input/touchscreen/ |
| D | ti,am3359-tsc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/input/touchscreen/ti,am3359-tsc.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Miquel Raynal <miquel.raynal@bootlin.com> 14 const: ti,am3359-tsc 17 description: Wires refer to application modes i.e. 4/5/8 wire touchscreen 22 ti,x-plate-resistance: 26 ti,coordinate-readouts: 33 minimum: 1 [all …]
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| /Documentation/devicetree/bindings/leds/backlight/ |
| D | kinetic,ktd253.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Kinetic Technologies KTD253 and KTD259 one-wire backlight 10 - Linus Walleij <linus.walleij@linaro.org> 16 using pulses on the enable wire. This is sometimes referred to as 20 - $ref: common.yaml# 25 - enum: 26 - kinetic,ktd253 27 - kinetic,ktd259 [all …]
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| /Documentation/devicetree/bindings/iio/adc/ |
| D | adi,ad7944.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Michael Hennerich <Michael.Hennerich@analog.com> 11 - Nuno Sá <nuno.sa@analog.com> 14 A family of pin-compatible single channel differential analog to digital 21 $ref: /schemas/spi/spi-peripheral-props.yaml# 26 - adi,ad7944 27 - adi,ad7985 28 - adi,ad7986 [all …]
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| /Documentation/devicetree/bindings/rtc/ |
| D | maxim-ds1302.txt | 1 * Maxim/Dallas Semiconductor DS-1302 RTC 5 The device uses the standard MicroWire half-duplex transfer timing. 12 - compatible : Should be "maxim,ds1302" 16 - reg : Should be address of the device chip select within 19 - spi-max-frequency : DS-1302 has 500 kHz if powered at 2.2V, 22 - spi-3wire : The device has a shared signal IN/OUT line. 24 - spi-lsb-first : DS-1302 requires least significant bit first 27 - spi-cs-high: DS-1302 has active high chip select line. This is 33 #address-cells = <1>; 34 #size-cells = <0>; [all …]
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| /Documentation/w1/ |
| D | w1-generic.rst | 2 Introduction to the 1-wire (w1) subsystem 5 The 1-wire bus is a simple master-slave bus that communicates via a single 6 signal wire (plus ground, so two wires). 18 - DS9490 usb device 19 - W1-over-GPIO 20 - DS2482 (i2c to w1 bridge) 21 - Emulated devices, such as a RS232 converter, parallel port adapter, etc 25 ------------------------------ 29 - sysfs entries for that w1 master are created 30 - the w1 bus is periodically searched for new slave devices [all …]
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| /Documentation/driver-api/gpio/ |
| D | intro.rst | 17 A "General Purpose Input/Output" (GPIO) is a flexible software-controlled 25 System-on-Chip (SOC) processors heavily rely on GPIOs. In some cases, every 26 non-dedicated pin can be configured as a GPIO; and most chips have at least 31 Most PC southbridges have a few dozen GPIO-capable pins (with only the BIOS 36 - Output values are writable (high=1, low=0). Some chips also have 38 value might be driven, supporting "wire-OR" and similar schemes for the 41 - Input values are likewise readable (1, 0). Some chips support readback 42 of pins configured as "output", which is very useful in such "wire-OR" 44 input de-glitch/debounce logic, sometimes with software controls. 46 - Inputs can often be used as IRQ signals, often edge triggered but [all …]
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| /Documentation/netlink/specs/ |
| D | netdev.yaml | 1 # SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 9 - 11 name: xdp-act 12 render-max: true 14 - 19 - 23 - 24 name: ndo-xmit 27 - 28 name: xsk-zerocopy [all …]
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