Searched +full:1 +full:- +full:cell (Results 1 – 25 of 488) sorted by relevance
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| /Documentation/devicetree/bindings/net/ |
| D | ibm,emac.txt | 8 correct clock-frequency property.
13 - device_type : "network"
15 - compatible : compatible list, contains 2 entries, first is
16 "ibm,emac-CHIP" where CHIP is the host ASIC (440gx,
18 "ibm,emac4". For Axon, thus, we have: "ibm,emac-axon",
20 - interrupts : <interrupt mapping for EMAC IRQ and WOL IRQ>
21 - reg : <registers mapping>
22 - local-mac-address : 6 bytes, MAC address
23 - mal-device : phandle of the associated McMAL node
24 - mal-tx-channel : 1 cell, index of the tx channel on McMAL associated
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| D | fsl,fman.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <Frank.Li@nxp.com>
13 Due to the fact that the FMan is an aggregation of sub-engines (ports, MACs,
19 - fsl,fman
26 cell-index:
31 The cell-index value may be used by the SoC, to identify the
33 there's a description of the cell-index use in each SoC:
35 - P1023:
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| D | broadcom-bcm87xx.txt | 5 "ethernet-phy-ieee802.3-c45"
9 - broadcom,c45-reg-init : one of more sets of 4 cells. The first cell
11 address within the MMD, the third cell contains a mask to be ANDed
12 with the existing register value, and the fourth cell is ORed with
13 he result to yield the new register value. If the third cell has a
18 ethernet-phy@5 {
20 compatible = "broadcom,bcm8706", "ethernet-phy-ieee802.3-c45";
21 interrupt-parent = <&gpio>;
25 * GPIO[1] Tx/Rx
28 broadcom,c45-reg-init = <1 0xc808 0xff8f 0x70>;
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| D | sunplus,sp7021-emac.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/net/sunplus,sp7021-emac.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Wells Lu <wellslutw@gmail.com>
19 const: sunplus,sp7021-emac
22 maxItems: 1
25 maxItems: 1
28 maxItems: 1
31 maxItems: 1
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| D | fsl,fman-dtsec.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/fsl,fman-dtsec.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Madalin Bucur <madalin.bucur@nxp.com>
15 10/100/1000 MBit/s speeds, and the 10-Gigabit Ethernet Media Access Controller
22 - fsl,fman-dtsec
23 - fsl,fman-xgec
24 - fsl,fman-memac
26 cell-index:
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | cdns,xtensa-pic.txt | 1 * Xtensa built-in Programmable Interrupt Controller (PIC)
4 - compatible: Should be "cdns,xtensa-pic".
5 - interrupt-controller: Identifies the node as an interrupt controller.
6 - #interrupt-cells: The number of cells to define the interrupts.
7 It may be either 1 or 2.
8 When it's 1, the first cell is the internal IRQ number.
9 When it's 2, the first cell is the IRQ number, and the second cell
10 specifies whether it's internal (0) or external (1).
18 compatible = "cdns,xtensa-pic";
19 /* one cell: internal irq number,
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| D | cdns,xtensa-mx.txt | 4 - compatible: Should be "cdns,xtensa-mx".
7 (see cdns,xtensa-pic.txt).
11 compatible = "cdns,xtensa-mx";
12 /* one cell: internal irq number,
13 * two cells: second cell == 0: internal irq number
14 * second cell == 1: external irq number
16 #interrupt-cells = <2>;
17 interrupt-controller;
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| /Documentation/devicetree/bindings/nvmem/layouts/ |
| D | fixed-cell.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/nvmem/layouts/fixed-cell.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Fixed offset & size NVMEM cell
10 - Rafał Miłecki <rafal@milecki.pl>
11 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
16 - const: mac-base
18 Cell with base MAC address to be used for calculating extra relative
20 It can be stored in a plain binary format (cell length 6) or as an
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| /Documentation/devicetree/bindings/mips/cavium/ |
| D | bootbus.txt | 7 - compatible: "cavium,octeon-3860-bootbus"
11 - reg: The base address of the Boot Bus' register bank.
13 - #address-cells: Must be <2>. The first cell is the chip select
14 within the bootbus. The second cell is the offset from the chip select.
16 - #size-cells: Must be <1>.
18 - ranges: There must be one one triplet of (child-bus-address,
19 parent-bus-address, length) for each active chip select. If the
27 - compatible: "cavium,octeon-3860-bootbus-config"
29 - cavium,cs-index: A single cell indicating the chip select that
32 - cavium,t-adr: A cell specifying the ADR timing (in nS).
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| /Documentation/devicetree/bindings/powerpc/fsl/ |
| D | mpic.txt | 14 - compatible
22 - reg
24 Value type: <prop-encoded-array>
29 - interrupt-controller
35 - #interrupt-cells
39 specifiers do not contain the interrupt-type or type-specific
42 - #address-cells
47 - pic-no-reset
53 configuration registers to a sane state-- masked or
60 - big-endian
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| D | dma.txt | 4 This is a little-endian 4-channel DMA controller, used in Freescale mpc83xx
9 - compatible : must include "fsl,elo-dma"
10 - reg : DMA General Status Register, i.e. DGSR which contains
12 - ranges : describes the mapping between the address space of the
14 - cell-index : controller index. 0 for controller @ 0x8100
15 - interrupts : interrupt specifier for DMA IRQ
17 - DMA channel nodes:
18 - compatible : must include "fsl,elo-dma-channel"
20 - reg : DMA channel specific registers
21 - cell-index : DMA channel index starts at 0.
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| /Documentation/devicetree/bindings/thermal/ |
| D | sprd-thermal.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/thermal/sprd-thermal.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Orson Zhai <orsonzhai@gmail.com>
11 - Baolin Wang <baolin.wang7@gmail.com>
12 - Chunyan Zhang <zhang.lyra@gmail.com>
14 $ref: thermal-sensor.yaml#
18 const: sprd,ums512-thermal
21 maxItems: 1
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| /Documentation/devicetree/bindings/clock/ |
| D | stericsson,u8500-clks.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/stericsson,u8500-clks.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ST-Ericsson DB8500 (U8500) clocks
10 - Ulf Hansson <ulf.hansson@linaro.org>
11 - Linus Walleij <linus.walleij@linaro.org>
14 DB8500 digital baseband system-on-chip and its siblings such as
16 itself, not off-chip clocks. There are four different on-chip
17 clocks - RTC (32 kHz), CPU clock (SMP TWD), PRCMU (power reset and
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| /Documentation/devicetree/bindings/powerpc/4xx/ |
| D | cpm.txt | 4 - compatible : compatible list, currently only "ibm,cpm"
5 - dcr-access-method : "native"
6 - dcr-reg : < DCR register range >
9 - er-offset : All 4xx SoCs with a CPM controller have
15 er-offset = <1>.
16 - unused-units : specifier consist of one cell. For each
17 bit in the cell, the corresponding bit
20 - idle-doze : specifier consist of one cell. For each
21 bit in the cell, the corresponding bit
24 - standby : specifier consist of one cell. For each
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| /Documentation/ABI/testing/ |
| D | sysfs-nvmem-cells | 1 What: /sys/bus/nvmem/devices/.../cells/<cell-name>
6 The "cells" folder contains one file per cell exposed by the
8 with <name> being the cell name and <where> its location in
11 the file is the size of the cell (when known). The content of
12 the file is the binary content of the cell (may sometimes be
19 hexdump -C /sys/bus/nvmem/devices/1-00563/cells/product-name@d,0
20 00000000 54 4e 34 38 4d 2d 50 2d 44 4e |TN48M-P-DN|
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| /Documentation/devicetree/bindings/iio/adc/ |
| D | sprd,sc2720-adc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/sprd,sc2720-adc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Baolin Wang <baolin.wang7@gmail.com>
18 - sprd,sc2720-adc
19 - sprd,sc2721-adc
20 - sprd,sc2723-adc
21 - sprd,sc2730-adc
22 - sprd,sc2731-adc
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| /Documentation/devicetree/bindings/reset/ |
| D | ti-syscon-reset.txt | 6 typically provided by means of memory-mapped I/O registers. These registers are
22 --------------------
23 - compatible : Should be,
24 "ti,k2e-pscrst"
25 "ti,k2l-pscrst"
26 "ti,k2hk-pscrst"
27 "ti,syscon-reset"
28 - #reset-cells : Should be 1. Please see the reset consumer node below
30 - ti,reset-bits : Contains the reset control register information
33 Cell #1 : offset of the reset assert control
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| D | intel,rcu-gw.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/reset/intel,rcu-gw.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dilip Kota <eswara.kota@linux.intel.com>
15 - intel,rcu-lgm
16 - intel,rcu-xrx200
20 maxItems: 1
22 intel,global-reset:
24 $ref: /schemas/types.yaml#/definitions/uint32-array
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| /Documentation/devicetree/bindings/firmware/ |
| D | cznic,turris-omnia-mcu.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/firmware/cznic,turris-omnia-mcu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marek Behún <kabel@kernel.org>
18 const: cznic,turris-omnia-mcu
22 maxItems: 1
25 maxItems: 1
27 interrupt-controller: true
29 '#interrupt-cells':
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| /Documentation/devicetree/bindings/gpio/ |
| D | microchip,pic32-gpio.txt | 4 - compatible: "microchip,pic32mzda-gpio"
5 - reg: Base address and length for the device.
6 - interrupts: The port interrupt shared by all pins.
7 - gpio-controller: Marks the port as GPIO controller.
8 - #gpio-cells: Two. The first cell is the pin number and
9 the second cell is used to specify the gpio polarity as defined in
10 defined in <dt-bindings/gpio/gpio.h>:
12 1 = GPIO_ACTIVE_LOW
14 - interrupt-controller: Marks the device node as an interrupt controller.
15 - #interrupt-cells: Two. The first cell is the GPIO number and second cell
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| D | gpio-twl4030.txt | 4 - compatible:
5 - "ti,twl4030-gpio" for twl4030 GPIO controller
6 - #gpio-cells : Should be two.
7 - first cell is the pin number
8 - second cell is used to specify optional parameters (unused)
9 - gpio-controller : Marks the device node as a GPIO controller.
10 - #interrupt-cells : Should be 2.
11 - interrupt-controller: Mark the device node as an interrupt controller
12 The first cell is the GPIO number.
13 The second cell is not used.
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| /Documentation/driver-api/ |
| D | nvmem.rst | 1 .. SPDX-License-Identifier: GPL-2.0
12 1. Introduction
20 register a sysfs file, allow in-kernel users to access the content of the
23 This was also a problem as far as other in-kernel users were involved, since
35 and write the non-volatile memory.
51 .name = "brcm-nvram",
55 config.dev = &pdev->dev;
74 .nvmem_name = "i2c-eeprom",
81 Additionally it is possible to create nvmem cell lookup entries and register
85 .nvmem_name = "i2c-eeprom",
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| /Documentation/devicetree/bindings/power/reset/ |
| D | nvmem-reboot-mode.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/power/reset/nvmem-reboot-mode.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
13 This driver gets the reboot mode magic value from the reboot-mode driver
14 and stores it in the NVMEM cell named "reboot-mode". The bootloader can
19 const: nvmem-reboot-mode
21 nvmem-cells:
23 A phandle pointing to the nvmem-cells node where the vendor-specific
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| /Documentation/devicetree/bindings/phy/ |
| D | sunplus,sp7021-usb2-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/phy/sunplus,sp7021-usb2-phy.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Vincent Shih <vincent.sunplus@gmail.com>
15 const: sunplus,sp7021-usb2-phy
19 - description: UPHY register region
20 - description: MOON4 register region
22 reg-names:
24 - const: phy
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| /Documentation/devicetree/bindings/mfd/ |
| D | tps65912.txt | 4 - compatible : Should be "ti,tps65912".
5 - reg : Slave address or chip select number (I2C / SPI).
6 - interrupts : The interrupt line the device is connected to.
7 - interrupt-controller : Marks the device node as an interrupt controller.
8 - #interrupt-cells : The number of cells to describe an IRQ, should be 2.
9 The first cell is the IRQ number.
10 The second cell is the flags, encoded as trigger
11 masks from ../interrupt-controller/interrupts.txt.
12 - gpio-controller : Marks the device node as a GPIO Controller.
13 - #gpio-cells : Should be two. The first cell is the pin number and
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