Home
last modified time | relevance | path

Searched +full:1 +full:- +full:of +full:- +full:4 (Results 1 – 25 of 1023) sorted by relevance

12345678910>>...41

/Documentation/input/devices/
Delantech.rst4 Copyright (C) 2007-2008 Arjan Opmeer <arjan@opmeer.net>
6 Extra information for hardware version 1 found and
15 1. Introduction
18 4. Hardware version 1
20 4.2 Native relative mode 4 byte packet format
21 4.3 Native absolute mode 4 byte packet format
25 5.2.1 Parity checking and packet re-synchronization
31 6.2.1 One/Three finger touch
33 7. Hardware version 4
36 7.2.1 Status packet
[all …]
Dalps.rst1 ----------------------
3 ----------------------
6 ------------
8 ALPS touchpads, called versions 1, 2, 3, 4, 5, 6, 7 and 8.
10 Since roughly mid-2010 several new ALPS touchpads have been released and
11 integrated into a variety of laptops and netbooks. These new touchpads
13 table, describing the properties of the different versions, is no longer
14 adequate. The design choices were to re-define the alps_model_data
15 table, with the risk of regression testing existing devices, or isolate
16 the new devices outside of the alps_model_data table. The latter design
[all …]
/Documentation/devicetree/bindings/scsi/
Dhisilicon-sas.txt6 - compatible : value should be as follows:
7 (a) "hisilicon,hip05-sas-v1" for v1 hw in hip05 chipset
8 (b) "hisilicon,hip06-sas-v2" for v2 hw in hip06 chipset
9 (c) "hisilicon,hip07-sas-v2" for v2 hw in hip07 chipset
10 - sas-addr : array of 8 bytes for host SAS address
11 - reg : Contains two regions. The first is the address and length of the SAS
12 register. The second is the address and length of CPLD register for
15 - hisilicon,sas-syscon: phandle of syscon used for sas control
16 - ctrl-reset-reg : offset to controller reset register in ctrl reg
17 - ctrl-reset-sts-reg : offset to controller reset status register in ctrl reg
[all …]
/Documentation/devicetree/bindings/net/
Dhisilicon-hns-dsaf.txt4 - compatible: should be "hisilicon,hns-dsaf-v1" or "hisilicon,hns-dsaf-v2".
5 "hisilicon,hns-dsaf-v1" is for hip05.
6 "hisilicon,hns-dsaf-v2" is for Hi1610 and Hi1612.
7 - mode: dsa fabric mode string. only support one of dsaf modes like these:
8 "2port-64vf",
9 "6port-16rss",
10 "6port-16vf",
11 "single-port".
12 - interrupts: should contain the DSA Fabric and rcb interrupt.
13 - reg: specifies base physical address(es) and size of the device registers.
[all …]
Dsamsung-sxgbe.txt4 - compatible: Should be "samsung,sxgbe-v2.0a"
5 - reg: Address and length of the register set for the device
6 - interrupts: Should contain the SXGBE interrupts
9 index 0 - this is fixed common interrupt of SXGBE and it is always
11 index 1 to 25 - 8 variable transmit interrupts, variable 16 receive interrupts
12 and 1 optional lpi interrupt.
13 - phy-mode: String, operation mode of the PHY interface.
15 - samsung,pbl: Integer, Programmable Burst Length.
16 Supported values are 1, 2, 4, 8, 16, or 32.
17 - samsung,burst-map: Integer, Program the possible bursts supported by sxgbe
[all …]
/Documentation/userspace-api/media/v4l/
Dmetafmt-vsp1-hgt.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _v4l2-meta-fmt-vsp1-hgt:
9 Renesas R-Car VSP1 2-D Histogram Data
15 This format describes histogram data generated by the Renesas R-Car VSP1
16 2-D Histogram (HGT) engine.
20 computes the sum, maximum and minimum of the S component as well as a
23 The histogram is a matrix of 6 Hue and 32 Saturation buckets, 192 in
25 between 1 and 16 depending on the Hue areas configuration. Finding the
28 The Saturation position **n** (0 - 31) of the bucket in the matrix is
33 The Hue position **m** (0 - 5) of the bucket in the matrix depends on
[all …]
Dpixfmt-yuv-planar.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. planar-yuv:
12 - Semi-planar formats use two planes. The first plane is the luma plane and
16 - Fully planar formats use three planes to store the Y, Cb and Cr components
20 tiled. Padding may be supported at the end of the lines, and the line stride of
21 the chroma planes may be constrained by the line stride of the luma plane.
26 and applications that support the multi-planar API, described in
27 :ref:`planar-apis`. Unless explicitly documented as supporting non-contiguous
31 Semi-Planar YUV Formats
40 For memory contiguous formats, the number of padding pixels at the end of the
[all …]
Dyuv-formats.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _yuv-formats:
11 and V or Cb and Cr). The color information consists of red and blue
25 advantage of the human eye being more sensitive to luminance than color
28 While many combinations of subsampling factors in the horizontal and vertical
29 direction are possible, common factors are 1 (no subsampling), 2 and 4, with
33 - `4:4:4`: No subsampling
34 - `4:2:2`: Horizontal subsampling by 2, no vertical subsampling
35 - `4:2:0`: Horizontal subsampling by 2, vertical subsampling by 2
36 - `4:1:1`: Horizontal subsampling by 4, no vertical subsampling
[all …]
Dpixfmt-rgb.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _pixfmt-rgb:
9 These formats encode each pixel as a triplet of RGB values. They are packed
11 memory and each pixel consumes an integer number of bytes. When the number of
15 The formats differ by the number of bits per RGB component (typically but not
16 always the same for all components), the order of components in memory, and the
17 presence of an alpha component or additional padding bits.
19 The usage and value of the alpha bits in formats that support them (named ARGB
22 (including capture queues of mem-to-mem devices) fill the alpha component in
25 but can set the alpha bit to a user-configurable value, the
[all …]
Dpixfmt-packed-yuv.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _packed-yuv:
15 - In all the tables that follow, bit 7 is the most significant bit in a byte.
16 - 'Y', 'Cb' and 'Cr' denote bits of the luma, blue chroma (also known as
18 denotes bits of the alpha component (if supported by the format), and 'X'
22 4:4:4 Subsampling
26 full triplet of Y, Cb and Cr values.
28 The next table lists the packed YUV 4:4:4 formats with less than 8 bits per
29 component. They are named based on the order of the Y, Cb and Cr components as
30 seen in a 16-bit word, which is then stored in memory in little endian byte
[all …]
/Documentation/devicetree/bindings/dma/
Dmilbeaut-m10v-hdmac.txt4 - device to memory transfer
5 - memory to device transfer
8 - compatible: Should be "socionext,milbeaut-m10v-hdmac"
9 - reg: Should contain DMA registers location and length.
10 - interrupts: Should contain all of the per-channel DMA interrupts.
11 Number of channels is configurable - 2, 4 or 8, so
12 the number of interrupts specified should be {2,4,8}.
13 - #dma-cells: Should be 1. Specify the ID of the slave.
14 - clocks: Phandle to the clock used by the HDMAC module.
19 hdmac1: dma-controller@1e110000 {
[all …]
Dsnps,dma-spear1340.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/dma/snps,dma-spear1340.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Viresh Kumar <vireshk@kernel.org>
11 - Andy Shevchenko <andriy.shevchenko@linux.intel.com>
14 - $ref: dma-controller.yaml#
19 - const: snps,dma-spear1340
20 - items:
21 - enum:
[all …]
Dsocionext,uniphier-mio-dmac.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/dma/socionext,uniphier-mio-dmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
14 - Masahiro Yamada <yamada.masahiro@socionext.com>
17 - $ref: dma-controller.yaml#
21 const: socionext,uniphier-mio-dmac
24 maxItems: 1
28 A list of interrupt specifiers associated with the DMA channels.
29 The number of interrupt lines is SoC-dependent.
[all …]
/Documentation/filesystems/ext4/
Dblocks.rst1 .. SPDX-License-Identifier: GPL-2.0
4 ------
6 ext4 allocates storage space in units of “blocks”. A block is a group of
7 sectors between 1KiB and 64KiB, and the number of sectors must be an
8 integral power of 2. Blocks are in turn grouped into larger units called
10 4KiB. You may experience mounting problems if block size is greater than
11 page size (i.e. 64KiB blocks on a i386 which only has 4KiB memory
14 of structures is stored in terms of the block number the structure lives
17 For 32-bit filesystems, limits are as follows:
19 .. list-table::
[all …]
/Documentation/core-api/
Dpacking.rst6 -----------------
8 When working with hardware, one has to choose between several approaches of
10 One can memory-map a pointer to a carefully crafted struct over the hardware
18 (sometimes even 64 bit ones). This creates the inconvenience of having to
19 define "high" and "low" portions of register fields within the struct.
21 required fields by shifting the appropriate number of bits. But this would
23 were performed byte-by-byte. Also the code can easily get cluttered, and the
24 high-level idea might get lost among the many bit shifts required.
25 Many drivers take the bit-shifting approach and then attempt to reduce the
30 ------------
[all …]
/Documentation/iio/
Dad7380.rst1 .. SPDX-License-Identifier: GPL-2.0-only
23 * `AD7380-4 <https://www.analog.com/en/products/ad7380-4.html>`_
24 * `AD7381-4 <https://www.analog.com/en/products/ad7381-4.html>`_
25 * `AD7383-4 <https://www.analog.com/en/products/ad7383-4.html>`_
26 * `AD7384-4 <https://www.analog.com/en/products/ad7384-4.html>`_
27 * `AD7386-4 <https://www.analog.com/en/products/ad7386-4.html>`_
28 * `AD7387-4 <https://www.analog.com/en/products/ad7387-4.html>`_
29 * `AD7388-4 <https://www.analog.com/en/products/ad7388-4.html>`_
36 ----------------
38 ad738x ADCs can output data on several SDO lines (1/2/4). The driver currently
[all …]
/Documentation/devicetree/bindings/crypto/
Dhisilicon,hip07-sec.txt4 - compatible: Must contain one of
5 - "hisilicon,hip06-sec"
6 - "hisilicon,hip07-sec"
7 - reg: Memory addresses and lengths of the memory regions through which
10 Region 1 has registers for functionality common to all queues.
11 Regions 2-18 have registers for the 16 individual queues which are isolated
13 - interrupts: Interrupt specifiers.
14 Refer to interrupt-controller/interrupts.txt for generic interrupt client node
17 Interrupt 2N + 1 is the completion interrupt for queue N.
19 - dma-coherent: The driver assumes coherent dma is possible.
[all …]
Dfsl,sec-v4.0.yaml1 # SPDX-License-Identifier: GPL-2.0
2 # Copyright (C) 2008-2011 Freescale Semiconductor Inc.
4 ---
5 $id: http://devicetree.org/schemas/crypto/fsl,sec-v4.0.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Freescale SEC 4
11 - '"Horia Geantă" <horia.geanta@nxp.com>'
12 - Pankaj Gupta <pankaj.gupta@nxp.com>
13 - Gaurav Jain <gaurav.jain@nxp.com>
16 NOTE: the SEC 4 is also known as Freescale's Cryptographic Accelerator
[all …]
/Documentation/networking/devlink/
Dice.rst1 .. SPDX-License-Identifier: GPL-2.0
13 .. list-table:: Generic parameters implemented
16 * - Name
17 - Mode
18 - Notes
19 * - ``enable_roce``
20 - runtime
21 - mutually exclusive with ``enable_iwarp``
22 * - ``enable_iwarp``
23 - runtime
[all …]
/Documentation/admin-guide/device-mapper/
Ddm-ebs.rst2 dm-ebs
8 size. Its main purpose is to provide emulation of 512 byte sectors on
9 devices that do not provide this emulation (i.e. 4K native disks).
13 Underlying block size can be set to > 4K to test buffering larger units.
17 ----------------
23 Full pathname to the underlying block-device,
24 or a "major:minor" device-number.
27 has to be a multiple of <emulated sectors>.
29 Number of sectors defining the logical block size to be emulated;
30 1, 2, 4, 8 sectors of 512 bytes supported.
[all …]
/Documentation/devicetree/bindings/interrupt-controller/
Dimg,pdc-intc.txt4 representation of a PDC IRQ controller. This has a number of input interrupt
10 - compatible: Specifies the compatibility list for the interrupt controller.
11 The type shall be <string> and the value shall include "img,pdc-intc".
13 - reg: Specifies the base PDC physical address(s) and size(s) of the
14 addressable register space. The type shall be <prop-encoded-array>.
16 - interrupt-controller: The presence of this property identifies the node
19 - #interrupt-cells: Specifies the number of cells needed to encode an
22 - num-perips: Number of waking peripherals.
24 - num-syswakes: Number of SysWake inputs.
26 - interrupts: List of interrupt specifiers. The first specifier shall be the
[all …]
/Documentation/devicetree/bindings/phy/
Dapm-xgene-phy.txt1 * APM X-Gene 15Gbps Multi-purpose PHY nodes
3 PHY nodes are defined to describe on-chip 15Gbps Multi-purpose PHY. Each
4 PHY (pair of lanes) has its own node.
7 - compatible : Shall be "apm,xgene-phy".
8 - reg : PHY memory resource is the SDS PHY access resource.
9 - #phy-cells : Shall be 1 as it expects one argument for setting
10 the mode of the PHY. Possible values are 0 (SATA),
11 1 (SGMII), 2 (PCIe), 3 (USB), and 4 (XFI).
14 - status : Shall be "ok" if enabled or "disabled" if disabled.
16 - clocks : Reference to the clock entry.
[all …]
/Documentation/sound/cards/
Dmaya44.rst6 The following is the original document of Rainer's patch that the
8 keep here as reference -- tiwai
14 STATE OF DEVELOPMENT
17 This driver is being developed on the initiative of Piotr Makowski (oponek@gmail.com) and financed …
22 … programming information, so I (Rainer Zimmermann) had to find out some card-specific information …
24 This is the first testing version of the Maya44 driver released to the alsa-devel mailing list (Feb…
29 - playback and capture at all sampling rates
30 - input/output level
31 - crossmixing
32 - line/mic switch
[all …]
/Documentation/trace/
Dhisi-ptt.rst1 .. SPDX-License-Identifier: GPL-2.0
17 On Kunpeng 930 SoC, the PCIe Root Complex is composed of several
19 RCiEP, like below. The PTT device is capable of tuning and
20 tracing the links of the PCIe core.
23 +--------------Core 0-------+
25 | | [Root Port]---[Endpoint]
26 | | [Root Port]---[Endpoint]
27 | | [Root Port]---[Endpoint]
28 Root Complex |------Core 1-------+
30 | | [Root Port]---[ Switch ]---[Endpoint]
[all …]
/Documentation/tools/rtla/
Drtla-hwnoise.rst1 .. SPDX-License-Identifier: GPL-2.0
4 rtla-hwnoise
6 ------------------------------------------
7 Detect and quantify hardware-related noise
8 ------------------------------------------
10 :Manual section: 1
22 of threads as a consequence, only non-maskable interrupts and hardware-related
25 The tool also allows the configurations of the *osnoise* tracer and the
26 collection of the tracer output.
38 In the example below, the **rtla hwnoise** tool is set to run on CPUs *1-7*
[all …]

12345678910>>...41