Searched +full:10 +full:- +full:bit (Results 1 – 25 of 483) sorted by relevance
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| /Documentation/i2c/ |
| D | ten-bit-addresses.rst | 2 I2C Ten-bit Addresses
5 The I2C protocol knows about two kinds of device addresses: normal 7 bit
6 addresses, and an extended set of 10 bit addresses. The sets of addresses
7 do not intersect: the 7 bit address 0x10 is not the same as the 10 bit
9 To avoid ambiguity, the user sees 10 bit addresses mapped to a different
10 address space, namely 0xa000-0xa3ff. The leading 0xa (= 10) represents the
11 10 bit mode. This is used for creating device names in sysfs. It is also
12 needed when instantiating 10 bit devices via the new_device file in sysfs.
14 I2C messages to and from 10-bit address devices have a different format.
17 The current 10 bit address support is minimal. It should work, however
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| /Documentation/gpu/ |
| D | afbc.rst | 1 .. SPDX-License-Identifier: GPL-2.0+
8 It provides fine-grained random access and minimizes the amount of
21 AFBC streams can contain several components - where a component
37 reside in the least-significant bits of the corresponding linear
81 Formats which are typically multi-planar in linear layouts (e.g. YUV
111 Cross-device interoperability
115 canonical formats for use between AFBC-enabled devices. Formats which
119 .. flat-table:: AFBC formats
121 * - Fourcc code
122 - Description
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| /Documentation/userspace-api/media/v4l/ |
| D | pixfmt-sdr-pcu18be.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _V4L2-SDR-FMT-PCU18BE:
9 Planar complex unsigned 18-bit big endian IQ sample
15 number consist of two parts called In-phase and Quadrature (IQ). Both I
16 and Q are represented as a 18 bit unsigned big endian number stored in
17 32 bit space. The remaining unused bits within the 32 bit space will be
20 the 18 bits, bit 17:2 (16 bit) is data and bit 1:0 (2 bit) can be any
26 .. flat-table::
27 :header-rows: 1
28 :stub-columns: 0
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| D | metafmt-generic.rst | 1 .. SPDX-License-Identifier: GPL-2.0 OR GFDL-1.1-no-invariants-or-later
8 Generic line-based metadata formats
14 These generic line-based metadata formats define the memory layout of the data
17 .. _v4l2-meta-fmt-generic-8:
20 -----------------------
22 The V4L2_META_FMT_GENERIC_8 format is a plain 8-bit metadata format. This format
23 is used on CSI-2 for 8 bits per :term:`Data Unit`.
26 packed into one 16-bit Data Unit. Otherwise the 16 bits per pixel dataformat is
27 :ref:`V4L2_META_FMT_GENERIC_CSI2_16 <v4l2-meta-fmt-generic-csi2-16>`.
34 .. flat-table:: Sample 4x2 Metadata Frame
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| D | pixfmt-inzi.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _V4L2-PIX-FMT-INZI:
9 Infrared 10-bit linked with Depth 16-bit images
15 Proprietary multi-planar format used by Intel SR300 Depth cameras, comprise of
16 Infrared image followed by Depth data. The pixel definition is 32-bpp,
22 The first plane - Infrared data - is stored according to
23 :ref:`V4L2_PIX_FMT_Y10 <V4L2-PIX-FMT-Y10>` greyscale format.
24 Each pixel is 16-bit cell, with actual data stored in the 10 LSBs
29 The second plane provides 16-bit per-pixel Depth data arranged in
30 :ref:`V4L2-PIX-FMT-Z16 <V4L2-PIX-FMT-Z16>` format.
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| D | pixfmt-z16.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _V4L2-PIX-FMT-Z16:
10 16-bit depth data with distance values at each pixel
16 This is a 16-bit format, representing depth data. Each pixel is a
19 is stored in a 16-bit word in the little endian byte order.
27 .. flat-table::
28 :header-rows: 0
29 :stub-columns: 0
31 * - start + 0:
32 - Z\ :sub:`00low`
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| /Documentation/devicetree/bindings/iio/adc/ |
| D | maxim,max1027.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Miquel Raynal <miquel.raynal@bootlin.com>
11 - Philippe Reynes <tremyfr@yahoo.fr>
19 # 10-bit 8 channels
20 - maxim,max1027
21 # 10-bit 12 channels
22 - maxim,max1029
23 # 10-bit 16 channels
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| /Documentation/devicetree/bindings/ |
| D | trivial-devices.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/trivial-devices.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
27 spi-max-frequency: true
32 - enum:
34 - acbel,fsg032
35 … # SMBus/I2C Digital Temperature Sensor in 6-Pin SOT with SMBus Alert and Over Temperature Pin
36 - ad,ad7414 # Deprecated, use adi,ad7414
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| /Documentation/ABI/testing/ |
| D | sysfs-driver-zynqmp-fpga | 1 What: /sys/bus/platform/drivers/zynqmp_fpga_manager/firmware:zynqmp-firmware:pcap/status
7 of the FPGA device. Each bit position in the status value is
9 https://docs.xilinx.com/v/u/en-US/ug570-ultrascale-configuration
12 BIT(0) 0: No CRC error
15 BIT(1) 0: Decryptor security not set
18 BIT(2) 0: MMCMs/PLLs are not locked
21 BIT(3) 0: DCI not matched
24 BIT(4) 0: Start-up sequence has not finished
25 1: Start-up sequence has finished
27 BIT(5) 0: All I/Os are placed in High-Z state
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| D | sysfs-class-rapidio | 3 On-chip RapidIO controllers and PCIe-to-RapidIO bridges
21 0 = small (8-bit destination ID, max. 256 devices),
23 1 = large (16-bit destination ID, max. 65536 devices).
46 [rio@rapidio ~]$ ls /sys/class/rapidio_port/rapidio0/ -l
48 drwxr-xr-x 3 root root 0 Feb 11 15:10 00:e:0001
49 drwxr-xr-x 3 root root 0 Feb 11 15:10 00:e:0004
50 drwxr-xr-x 3 root root 0 Feb 11 15:10 00:e:0007
51 drwxr-xr-x 3 root root 0 Feb 11 15:10 00:s:0002
52 drwxr-xr-x 3 root root 0 Feb 11 15:10 00:s:0003
53 drwxr-xr-x 3 root root 0 Feb 11 15:10 00:s:0005
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| /Documentation/core-api/ |
| D | packing.rst | 6 -----------------
10 One can memory-map a pointer to a carefully crafted struct over the hardware
15 definitions from the hardware documentation into bit field indices for the
18 (sometimes even 64 bit ones). This creates the inconvenience of having to
23 were performed byte-by-byte. Also the code can easily get cluttered, and the
24 high-level idea might get lost among the many bit shifts required.
25 Many drivers take the bit-shifting approach and then attempt to reduce the
30 ------------
34 - Packing a CPU-usable number into a memory buffer (with hardware
36 - Unpacking a memory buffer (which has hardware constraints/quirks)
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| /Documentation/devicetree/bindings/iio/dac/ |
| D | lltc,ltc1660.yaml | 1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Linear Technology Micropower octal 8-Bit and 10-Bit DACs
11 - Marcus Folkesson <marcus.folkesson@gmail.com>
14 Bindings for the Linear Technology Micropower octal 8-Bit and 10-Bit DAC.
15 …Datasheet can be found here: https://www.analog.com/media/en/technical-documentation/data-sheets/1…
20 - lltc,ltc1660
21 - lltc,ltc1665
26 spi-max-frequency:
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| D | microchip,mcp4821.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
13 +---------+--------------+-------------+
15 |---------|--------------|-------------|
16 | MCP4801 | 8-bit | 1 |
17 | MCP4802 | 8-bit | 2 |
18 | MCP4811 | 10-bit | 1 |
19 | MCP4812 | 10-bit | 2 |
20 | MCP4821 | 12-bit | 1 |
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| /Documentation/devicetree/bindings/mfd/ |
| D | mc13xxx.txt | 4 - compatible : Should be "fsl,mc13783" or "fsl,mc13892"
7 - fsl,mc13xxx-uses-adc : Indicate the ADC is being used
8 - fsl,mc13xxx-uses-codec : Indicate the Audio Codec is being used
9 - fsl,mc13xxx-uses-rtc : Indicate the RTC is being used
10 - fsl,mc13xxx-uses-touch : Indicate the touchscreen controller is being used
12 Sub-nodes:
13 - codec: Contain the Audio Codec node.
14 - adc-port: Contain PMIC SSI port number used for ADC.
15 - dac-port: Contain PMIC SSI port number used for DAC.
16 - leds : Contain the led nodes and initial register values in property
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| /Documentation/devicetree/bindings/display/ |
| D | simple-framebuffer.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/simple-framebuffer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Hans de Goede <hdegoede@redhat.com>
13 A simple frame-buffer describes a frame-buffer setup by firmware or
19 sub-nodes of the chosen node (*). Simplefb nodes must be named
41 interaction, then the chosen node stdout-path property should point
46 It is advised that devicetree files contain pre-filled, disabled
52 If pre-filled framebuffer nodes are used, the firmware may need
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| /Documentation/networking/ |
| D | oa-tc6-framework.rst | 1 .. SPDX-License-Identifier: GPL-2.0+
4 OPEN Alliance 10BASE-T1x MAC-PHY Serial Interface (TC6) Framework Support
8 ------------
10 The IEEE 802.3cg project defines two 10 Mbit/s PHYs operating over a
11 single pair of conductors. The 10BASE-T1L (Clause 146) is a long reach
12 PHY supporting full duplex point-to-point operation over 1 km of single
13 balanced pair of conductors. The 10BASE-T1S (Clause 147) is a short reach
14 PHY supporting full / half duplex point-to-point operation over 15 m of
21 works in conjunction with the 10BASE-T1S PHY operating in multidrop mode.
23 The aforementioned PHYs are intended to cover the low-speed / low-cost
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| /Documentation/devicetree/bindings/sound/ |
| D | qcom,lpass-cpu.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/qcom,lpass-cpu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
11 - Rohit kumar <quic_rohkumar@quicinc.com>
14 Qualcomm Technologies Inc. SOC Low-Power Audio SubSystem (LPASS) that consist
16 is a module to configure Low-Power Audio Interface(LPAIF) core registers
22 - qcom,lpass-cpu
23 - qcom,apq8016-lpass-cpu
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| /Documentation/scsi/ |
| D | aic7xxx.rst | 1 .. SPDX-License-Identifier: GPL-2.0
5 Adaptec Aic7xxx Fast -> Ultra160 Family Manager Set v7.0
26 aic7770 10 EISA/VL 10MHz 16Bit 4 1
27 aic7850 10 PCI/32 10MHz 8Bit 3
28 aic7855 10 PCI/32 10MHz 8Bit 3
29 aic7856 10 PCI/32 10MHz 8Bit 3
30 aic7859 10 PCI/32 20MHz 8Bit 3
31 aic7860 10 PCI/32 20MHz 8Bit 3
32 aic7870 10 PCI/32 10MHz 16Bit 16
33 aic7880 10 PCI/32 20MHz 16Bit 16
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| /Documentation/hwmon/ |
| D | da9055.rst | 14 -----------
16 The DA9055 provides an Analogue to Digital Converter (ADC) with 10 bits
24 - Channel 0: VDDOUT - measurement of the system voltage
25 - Channel 1: ADC_IN1 - high impedance input (0 - 2.5V)
26 - Channel 2: ADC_IN2 - high impedance input (0 - 2.5V)
27 - Channel 3: ADC_IN3 - high impedance input (0 - 2.5V)
28 - Channel 4: Internal Tjunc. - sense (internal temp. sensor)
34 ------------------
37 are stored in a 10 bit ADC.
48 ----------------------
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| /Documentation/devicetree/bindings/net/ |
| D | fsl,fman-dtsec.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/fsl,fman-dtsec.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Madalin Bucur <madalin.bucur@nxp.com>
15 10/100/1000 MBit/s speeds, and the 10-Gigabit Ethernet Media Access Controller
16 (10GEC) for 10 Gbit/s speeds. Later versions of FMan use the Multirate
22 - fsl,fman-dtsec
23 - fsl,fman-xgec
24 - fsl,fman-memac
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| /Documentation/devicetree/bindings/pinctrl/ |
| D | sprd,sc9860-pinctrl.txt | 7 - compatible: Must be "sprd,sc9860-pinctrl".
8 - reg: The register address of pin controller device.
9 - pins : An array of strings, each string containing the name of a pin.
12 - function: A string containing the name of the function, values must be
14 - drive-strength: Drive strength in mA. Supported values: 2, 4, 6, 8, 10,
16 - input-schmitt-disable: Enable schmitt-trigger mode.
17 - input-schmitt-enable: Disable schmitt-trigger mode.
18 - bias-disable: Disable pin bias.
19 - bias-pull-down: Pull down on pin.
20 - bias-pull-up: Pull up on pin. Supported values: 20000 for pull-up resistor
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| /Documentation/arch/powerpc/ |
| D | associativity.rst | 9 are represented as being members of a sub-grouping domain. This performance
17 Hypervisor indicates the type/form of associativity used via "ibm,architecture-vec-5 property".
18 Bit 0 of byte 5 in the "ibm,architecture-vec-5" property indicates usage of Form 0 or Form 1.
20 bit 2 of byte 5 in the "ibm,architecture-vec-5" property is used.
23 ------
27 ------
28 With Form 1 a combination of ibm,associativity-reference-points, and ibm,associativity
34 The “ibm,associativity-reference-points” property contains a list of one or more numbers
43 if they belong to the same higher-level domains. For mismatch at every higher
48 -------
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| /Documentation/devicetree/bindings/watchdog/ |
| D | men-a021-wdt.txt | 4 - compatible: "men,a021-wdt"
5 - gpios: Specifies the pins that control the Watchdog, order:
7 2: Watchdog fast-mode
9 4: Watchdog reset cause bit 0
10 5: Watchdog reset cause bit 1
11 6: Watchdog reset cause bit 2
14 - None
18 compatible ="men,a021-wdt";
20 &gpio3 10 1 /* WD_FAST */
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| /Documentation/arch/arm/pxa/ |
| D | mfp.rst | 7 MFP stands for Multi-Function Pin, which is the pin-mux logic on PXA3xx and
15 mechanism is introduced from PXA3xx to completely move the pin-mux functions
16 out of the GPIO controller. In addition to pin-mux configurations, the MFP
17 also controls the low power state, driving strength, pull-up/down and event
21 +--------+
22 | |--(GPIO19)--+
24 | |--(GPIO...) |
25 +--------+ |
26 | +---------+
27 +--------+ +------>| |
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| /Documentation/devicetree/bindings/timer/ |
| D | nvidia,tegra186-timer.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/nvidia,tegra186-timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <treding@nvidia.com>
13 The Tegra timer provides 29-bit timer counters and a 32-bit timestamp
16 programmed to generate one-shot, periodic, or watchdog interrupts.
22 - const: nvidia,tegra186-timer
24 The Tegra186 timer provides ten 29-bit timer counters.
25 - const: nvidia,tegra234-timer
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