Searched +full:100 +full:mhz (Results 1 – 25 of 65) sorted by relevance
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| /Documentation/fb/ |
| D | viafb.modes | 10 # 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock)
29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
35 # 640x480, 75 Hz, Non-Interlaced (31.50 MHz dotclock)
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
56 # 640x480, 85 Hz, Non-Interlaced (36.000 MHz dotclock)
74 # D: 36.000 MHz, H: 43.269 kHz, V: 85.00 Hz
77 # 640x480, 100 Hz, Non-Interlaced (43.163 MHz dotclock)
94 mode "640x480-100"
95 # D: 43.163 MHz, H: 50.900 kHz, V: 100.00 Hz
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| /Documentation/devicetree/bindings/net/ |
| D | qcom,ipq4019-mdio.yaml | 42 - description: MDIO clock source frequency fixed to 100MHZ
53 MDC rate is feed by an external clock (fixed 100MHz) and is divider
57 To follow 802.3 standard that instruct up to 2.5MHz by default, if
59 default 1.5625Mhz is select.
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| D | micrel.txt | 23 - micrel,rmii-reference-clock-select-25-mhz: RMII Reference Clock Select
24 bit selects 25 MHz mode
26 Setting the RMII Reference Clock Select bit enables 25 MHz rather
27 than 50 MHz clock mode.
48 100base-fx (full and half duplex) modes.
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| D | ti,dp83822.yaml | 14 The DP83822 is a low-power, single-port, 10/100 Mbps Ethernet PHY. It
49 100base-fx (full and half duplex) modes.
87 - RMII master, where the PHY outputs a 50MHz reference clock which can
89 - RMII slave, where the PHY expects a 50MHz reference clock input
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| D | amlogic,g12a-mdio-mux.yaml | 11 the internal mdio bus leading to the embedded 10/100 PHY or the external
31 - description: SoC 50MHz MPLL
76 max-speed = <100>;
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| D | wiznet,w5x00.txt | 3 This is a standalone 10/100 MBit Ethernet controller with SPI interface.
25 According to the w5500 datasheet, the chip allows a maximum of 80 MHz, however,
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| D | xlnx,gmii-to-rgmii.yaml | 16 This core can be used in all three modes of operation(10/100/1000 Mb/s).
36 - description: 200/375 MHz free-running clock is used as input clock.
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| D | rockchip-dwmac.yaml | 7 title: Rockchip 10/100/1000 Ethernet driver(GMAC)
79 For RGMII, it must be "input", means main clock(125MHz)
81 For RMII, "input" means PHY provides the reference clock(50MHz),
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| /Documentation/devicetree/bindings/cpu/ |
| D | cpu-capacity.txt | 38 by the frequency (in MHz) at which the benchmark has been run, so that
39 DMIPS/MHz are obtained. Such values are then normalized w.r.t. the highest
43 3 - capacity-dmips-mhz
46 capacity-dmips-mhz is an optional cpu node [1] property: u32 value
47 representing CPU capacity expressed in normalized DMIPS/MHz. At boot time, the
51 capacity-dmips-mhz property is all-or-nothing: if it is specified for a cpu
55 mhz values (normalized w.r.t. the highest value found while parsing the DT).
62 The capacities-dmips-mhz or DMIPS/MHz values (scaled to 1024)
105 entry-latency-us = <100>;
128 capacity-dmips-mhz = <1024>;
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| /Documentation/devicetree/bindings/pinctrl/ |
| D | intel,pinctrl-keembay.yaml | 78 0 - Fast(~100MHz)
79 1 - Slow(~50MHz)
112 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
132 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
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| /Documentation/admin-guide/pm/ |
| D | intel-speed-select.rst | 154 base-frequency(MHz):2600
168 condition is met, then base frequency of 2600 MHz can be maintained. To
183 base-frequency(MHz):2800
211 This matches the base-frequency (MHz) field value displayed from the
215 To check if the average frequency is equal to the base frequency for a 100% busy
261 Which shows that the base frequency now increased from 2600 MHz at performance
262 level 0 to 2800 MHz at performance level 4. As a result, any workload, which can
263 use fewer CPUs, can see a boost of 200 MHz compared to performance level 0.
424 Specify clos min in MHz with [--min|-n]
425 Specify clos max in MHz with [--max|-m]
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| D | intel_uncore_frequency_scaling.rst | 144 in 100MHz steps. This avoids consuming unnecessarily high power
167 * when CPU utilization is less than 10%: sets uncore frequency to 800MHz
169 100MHz steps, until power limit is reached
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| /Documentation/i2c/busses/ |
| D | i2c-ali15x3.rst | 52 100MHz CPU Front Side bus
53 * "Aladdin V" includes the M1541 Socket 7 North bridge with AGP and 100MHz
68 with host bus up to 83.3 MHz.
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| /Documentation/networking/dsa/ |
| D | sja1105.rst | 16 - SJA1110A: Third generation, TTEthernet, SGMII, integrated 100base-T1 and
17 100base-TX PHYs
18 - SJA1110B: Third generation, TTEthernet, SGMII, 100base-T1, 100base-TX
19 - SJA1110C: Third generation, TTEthernet, SGMII, 100base-T1, 100base-TX
20 - SJA1110D: Third generation, TTEthernet, SGMII, 100base-T1
135 ``swp5``. The traffic class gate for management traffic (7) is open for 100 us,
165 tc qdisc add dev swp5 parent root handle 100 taprio \
214 of 100 and a PCP of 0::
217 dst_mac 42:be:24:9b:76:20 vlan_id 100 vlan_prio 0 action drop
332 In the RMII spec, the 50 MHz clock signals are either driven by the MAC or by
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| /Documentation/devicetree/bindings/phy/ |
| D | phy-rockchip-naneng-combphy.yaml | 59 By default the internal clock is selected. The PCIe PHY provides a 100MHz
61 When selecting this option an externally 100MHz differential
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| /Documentation/devicetree/bindings/net/can/ |
| D | cc770.txt | 3 Note: The CC770 is a CAN controller from Bosch, which is 100%
22 value of 16000000 (16 MHz) is used.
47 can@3,100 {
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| /Documentation/devicetree/bindings/i2c/ |
| D | i2c-exynos5.yaml | 14 at various speeds ranging from 100kHz to 3.4MHz.
53 If not specified, the bus operates in fast-speed mode at 100kHz.
56 clock-frequency is >= 1MHz.
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| /Documentation/devicetree/bindings/thermal/ |
| D | thermal-idle.yaml | 66 cpu_b0: cpu@100 {
71 capacity-dmips-mhz = <1024>;
87 capacity-dmips-mhz = <1024>;
106 polling-delay-passive = <100>;
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| /Documentation/devicetree/bindings/watchdog/ |
| D | cdns,wdt-r1p2.yaml | 16 to 30 seconds while using a 100Mhz clock.
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| /Documentation/networking/device_drivers/ethernet/chelsio/ |
| D | cxgb.rst | 60 An example to set the timer latency value to 100us on eth0::
62 ethtool -C eth0 rx-usecs 100
188 Example for RTT with 100us: RX_WINDOW = (1,250,000 * 0.1) = 125,000
221 eth#: Chelsio N210 1x10GBaseX NIC (rev #), PCIX 133MHz/64-bit
307 chipset, you may experience the "133-Mhz Mode Split Completion Data
308 Corruption" bug identified by AMD while using a 133Mhz PCI-X card on the
313 is operating at 133 Mhz", causing data corruption.
318 For 133Mhz secondary bus operation, limit the transaction length and
327 section 56, "133-MHz Mode Split Completion Data Corruption" for more
377 Suite 100
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| /Documentation/devicetree/bindings/media/i2c/ |
| D | dongwoon,dw9768.yaml | 15 with 100 mA output current sink capability. VCM current is controlled with
17 serial interface that operates at clock rates up to 1MHz. This chip
52 vibration register AACT[5:0], the unit of which is 100 us.
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| /Documentation/devicetree/bindings/mfd/ |
| D | st,stmpe.yaml | 79 0 = 1.625 MHz
80 1 = 3.25 MHz
81 2, 3 = 6.5 MHz
157 2 = 100 us
170 1 = 100 us
176 7 = 100 ms
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| /Documentation/devicetree/bindings/mmc/ |
| D | sdhci-st.txt | 41 - max-frequency: Can be 200MHz, 100MHz or 50MHz (default) and used for
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| D | amlogic,meson-mx-sdhc.yaml | 18 It supports eMMC spec 4.4x/4.5x including HS200 (up to 100MHz clock).
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| /Documentation/usb/ |
| D | iuu_phoenix.rst | 39 1=3Mhz579,2=3Mhz680,3=6Mhz (int)
41 overclock boost percent 100 to 500 (int)
55 3. 6Mhz
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