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/Documentation/fb/
Dviafb.modes14 # Scan Frequency 31.469 kHz 59.94 Hz
29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
39 # Scan Frequency 37.500 kHz 75.00 Hz
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
60 # Scan Frequency 43.269 kHz 85.00 Hz
74 # D: 36.000 MHz, H: 43.269 kHz, V: 85.00 Hz
77 # 640x480, 100 Hz, Non-Interlaced (43.163 MHz dotclock)
81 # Scan Frequency 50.900 kHz 100.00 Hz
94 mode "640x480-100"
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/Documentation/i2c/busses/
Di2c-ismt.rst21 Specify the bus speed in kHz.
27 80 kHz
28 100 kHz
29 400 kHz
30 1000 kHz
/Documentation/hwmon/
Dmcp3021.rst36 compatible interface. Standard (100 kHz) and Fast (400 kHz) I2C modes are
Dlm85.rst153 driven by a 22.5 kHz clock. This is a global mode, not per-PWM output,
154 which means that setting any PWM frequency above 11.3 kHz will switch
155 all 3 PWM outputs to a 22.5 kHz frequency. Conversely, setting any PWM
156 frequency below 11.3 kHz will switch all 3 PWM outputs to a frequency
157 between 10 and 100 Hz, which can then be tuned separately.
179 The LM96000 supports additional high frequency PWM modes (22.5 kHz, 24 kHz,
180 25.7 kHz, 27.7 kHz and 30 kHz), which can be configured on a per-PWM basis.
266 -1 PWM always 100% (full on)
Df71805f.rst85 in2 VIN2 VRAM 100K 100K 2.00 ~1.25 V [1]_
86 in3 VIN3 VCHIPSET 47K 100K 1.47 2.24 V [2]_
150 from 187.5 kHz (default) to 31 Hz. The best frequency depends on the
153 above the audible range, such as 25 kHz, may be a good choice; if this
155 not going below 1 kHz, as the fan tachometers get confused by lower
/Documentation/devicetree/bindings/i2c/
Di2c-digicolor.txt13 absence of this property the default value is used (100 kHz).
Di2c-exynos5.yaml14 at various speeds ranging from 100kHz to 3.4MHz.
53 If not specified, the bus operates in fast-speed mode at 100kHz.
Di2c-axxia.txt15 the default 100 kHz frequency will be used. As only Normal and Fast modes
Daspeed,i2c.yaml44 description: frequency of the bus clock in Hz defaults to 100 kHz when not
Dopencores,i2c-ocores.yaml45 frequency is fixed at 100 KHz.
109 clock-frequency = <400000>; /* i2c bus frequency 400 KHz */
Dapple,i2c.yaml42 Desired I2C bus clock frequency in Hz. If not specified, 100 kHz will be
Dnuvoton,npcm7xx-i2c.yaml35 the default 100 kHz frequency will be used.
Di2c-rk3x.yaml81 SCL frequency to use (in Hz). If omitted, 100kHz is used.
139 i2c-scl-falling-time-ns = <100>;
Drenesas,riic.yaml62 indicates the default frequency 100 kHz.
Di2c-mt65xx.yaml89 SCL frequency to use (in Hz). If omitted, 100kHz is used.
Drenesas,rmobile-iic.yaml58 indicates the default frequency 100 kHz.
/Documentation/devicetree/bindings/rtc/
Dingenic,rtc.yaml68 (assuming RTC clock at 32 kHz)
73 default: 100
76 (assuming RTC clock at 32 kHz)
/Documentation/devicetree/bindings/tpm/
Dtcg,tpm-tis-i2c.yaml42 - infineon,slb9635tt # TPM 1.2 (maximum 100 kHz)
43 - infineon,slb9645tt # TPM 1.2 (maximum 400 kHz)
/Documentation/devicetree/bindings/hwmon/
Dadt7475.yaml45 the pwm uses a logic low output for 100% duty cycle. If set to 1 the pwm
46 uses a logic high output for 100% duty cycle.
69 - 44444 (22 kHz)
129 /* PWMs at 22.5 kHz frequency, 50% duty*/
/Documentation/devicetree/bindings/net/
Dqcom,ipq4019-mdio.yaml42 - description: MDIO clock source frequency fixed to 100MHZ
53 MDC rate is feed by an external clock (fixed 100MHz) and is divider
55 applied of 390KHz.
/Documentation/devicetree/bindings/sound/
Dcs35l33.txt23 a value of 1 and will increase at a step size of 100mV until a maximum of
32 60ms,100ms,175ms respectively for 48KHz sample rate.
72 from 0 to 7 for delays of 5ms, 10ms, 50ms, 100ms, 200ms, 500ms, 1000ms.
73 The default is 100ms.
81 by 100mV per step to a maximum of 5500mV.
/Documentation/devicetree/bindings/iio/pressure/
Dhoneywell,hsc030pa.yaml31 exceed 800kHz and the MOSI signal is not required.
64 006MD, 010MD, 016MD, 025MD, 040MD, 060MD, 100MD, 160MD, 250MD,
66 010MG, 016MG, 025MG, 040MG, 060MG, 100MG, 160MG, 250MG, 400MG,
67 600MG, 001BG, 1.6BG, 2.5BG, 004BG, 006BG, 010BG, 100KA, 160KA,
70 100KD, 160KD, 250KD, 400KD, 250LG, 400LG, 600LG, 001KG, 1.6KG,
71 2.5KG, 004KG, 006KG, 010KG, 016KG, 025KG, 040KG, 060KG, 100KG,
72 160KG, 250KG, 400KG, 600KG, 001GG, 015PA, 030PA, 060PA, 100PA,
75 010NG, 020NG, 030NG, 001PG, 005PG, 015PG, 030PG, 060PG, 100PG,
/Documentation/admin-guide/pm/
Dcpufreq.rst245 the hardware (in KHz).
253 can run at (in kHz).
257 can run at (in kHz).
272 (in kHz).
285 Current frequency of all of the CPUs belonging to this policy (in kHz).
315 running at (in kHz).
323 running at (in kHz).
333 It returns the last frequency requested by the governor (in kHz) or can
466 1 (or 100%), and the value of the ``cpuinfo_min_freq`` policy attribute
506 Temporary multiplier, between 1 (default) and 100 inclusive, to apply to
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/Documentation/admin-guide/media/
Dvivid.rst332 configuration of your kernel, so usually 1/100, 1/250 or 1/1000 of a second),
391 ioctl will return 100% signal strength for +/- 0.25 MHz and 50% for +/- 1 MHz.
499 Aspect Ratio control setting and teletext pages 100-159, one page per frame.
526 - AM: 520 kHz - 1710 kHz
527 - SW: 2300 kHz - 26.1 MHz
529 Valid channels are emulated every 1 MHz for FM and every 100 kHz for AM and SW.
531 frequency until it becomes 0% at +/- 50 kHz (FM) or 5 kHz (AM/SW) from the
541 The RDS signal is 'detected' for +/- 12.5 kHz around the channel frequency,
544 blocks if you are +/- 12.5 kHz from the channel frequency. All four errors
562 - AM: 520 kHz - 1710 kHz
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/Documentation/devicetree/bindings/input/
Diqs269a.yaml183 3: 2 MHz (500 kHz)
390 1: 2 MHz (500 kHz)
391 2: 1 MHz (250 kHz)
392 3: 500 kHz (125 kHz)
411 enum: [75, 100, 150, 200]
412 default: 100

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