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| /Documentation/translations/zh_CN/core-api/ |
| D | packing.rst | 1 .. SPDX-License-Identifier: GPL-2.0+
3 .. include:: ../disclaimer-zh_CN.rst
5 :Original: Documentation/core-api/packing.rst
22 --------
42 --------
46 - 将一个CPU可使用的数字打包到内存缓冲区中（具有硬件约束/特殊性）。
47 - 将内存缓冲区（具有硬件约束/特殊性）解压缩为一个CPU可使用的数字。
63 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
77 24 25 26 27 28 29 30 31 16 17 18 19 20 21 22 23 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7
89 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 23 22 21 20 19 18 17 16 31 30 29 28 27 26 25 24
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| /Documentation/devicetree/bindings/pci/ |
| D | v3-v360epc-pci.txt | 6 - compatible: should be one of:
7 "v3,v360epc-pci"
8 "arm,integrator-ap-pci", "v3,v360epc-pci"
9 - reg: should contain two register areas:
12 - interrupts: should contain a reference to the V3 error interrupt
14 - bus-range: see pci.txt
15 - ranges: this follows the standard PCI bindings in the IEEE Std
16 1275-1994 (see pci.txt) with the following restriction:
17 - The non-prefetchable and prefetchable memory windows must
19 - The prefetchable memory window must be immediately adjacent
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| D | qcom,pcie-common.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/qcom,pcie-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <andersson@kernel.org>
11 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
18 reg-names:
26 interrupt-names:
30 iommu-map:
36 maxItems: 13
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| /Documentation/tools/rtla/ |
| D | rtla-timerlat-top.rst | 2 rtla-timerlat-top
4 -------------------------------------------
6 -------------------------------------------
22 seem with the option **-T**.
35 **--aa-only** *us*
38 Print the auto-analysis if the system hits the stop tracing condition. This option
45 In the example below, the timerlat tracer is dispatched in cpus *1-23* in the
49 # timerlat -a 40 -c 1-23 -q
51 0 00:00:12 | IRQ Timer Latency (us) | Thread Timer Latency (us)
54 2 #12322 | 3 0 1 12 | 10 3 9 23
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| D | rtla-timerlat-hist.rst | 2 rtla-timerlat-hist
4 ------------------------------------------------
6 ------------------------------------------------
21 **osnoise:** tracepoints are enabled when using the **-T** option.
37 in the cpus *0-4*, *skipping zero* only lines. Moreover, **rtla timerlat
40 *1ms* period is also passed to the *timerlat* tracer. Auto-analysis is disabled
43 [root@alien ~]# timerlat hist -d 10m -c 0-4 -P d:100us:1ms -p 1000 --no-aa
47 …Index IRQ-000 Thr-000 IRQ-001 Thr-001 IRQ-002 Thr-002 IRQ-003 Thr-003 IRQ-004 …
57 …9 22 10387 12 42762 161 2554 225 2689 19 …
58 …10 13 1898 8 5770 114 1247 128 1405 13 …
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| /Documentation/core-api/ |
| D | packing.rst | 6 -----------------
10 One can memory-map a pointer to a carefully crafted struct over the hardware
23 were performed byte-by-byte. Also the code can easily get cluttered, and the
24 high-level idea might get lost among the many bit shifts required.
25 Many drivers take the bit-shifting approach and then attempt to reduce the
30 ------------
34 - Packing a CPU-usable number into a memory buffer (with hardware
36 - Unpacking a memory buffer (which has hardware constraints/quirks)
37 into a CPU-usable number.
57 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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| /Documentation/userspace-api/media/v4l/ |
| D | pixfmt-yuv-planar.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. planar-yuv:
12 - Semi-planar formats use two planes. The first plane is the luma plane and
16 - Fully planar formats use three planes to store the Y, Cb and Cr components
26 and applications that support the multi-planar API, described in
27 :ref:`planar-apis`. Unless explicitly documented as supporting non-contiguous
31 Semi-Planar YUV Formats
46 For non-contiguous formats, no constraints are enforced by the format on the
57 .. flat-table:: Overview of Semi-Planar YUV Formats
58 :header-rows: 1
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| D | pixfmt-y8i.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _V4L2-PIX-FMT-Y8I:
10 Interleaved grey-scale image, e.g. from a stereo-pair
16 This is a grey-scale image with a depth of 8 bits per pixel, but with
17 pixels from 2 sources interleaved. Each pixel is stored in a 16-bit
27 .. flat-table::
28 :header-rows: 0
29 :stub-columns: 0
31 * - start + 0:
32 - Y'\ :sub:`00left`
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| D | pixfmt-z16.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _V4L2-PIX-FMT-Z16:
10 16-bit depth data with distance values at each pixel
16 This is a 16-bit format, representing depth data. Each pixel is a
19 is stored in a 16-bit word in the little endian byte order.
27 .. flat-table::
28 :header-rows: 0
29 :stub-columns: 0
31 * - start + 0:
32 - Z\ :sub:`00low`
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| D | pixfmt-tch-tu16.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _V4L2-TCH-FMT-TU16:
11 16-bit unsigned little endian raw touch data
17 This format represents unsigned 16-bit data from a touch controller.
26 .. flat-table::
27 :header-rows: 0
28 :stub-columns: 0
31 * - start + 0:
32 - R'\ :sub:`00low`
33 - R'\ :sub:`00high`
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| D | pixfmt-srggb12.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _V4L2-PIX-FMT-SRGGB12:
4 .. _v4l2-pix-fmt-sbggr12:
5 .. _v4l2-pix-fmt-sgbrg12:
6 .. _v4l2-pix-fmt-sgrbg12:
17 12-bit Bayer formats expanded to 16 bits
23 These four pixel formats are raw sRGB / Bayer formats with 12 bits per
24 colour. Each colour component is stored in a 16-bit word, with 4 unused
25 high bits filled with zeros. Each n-pixel row contains n/2 green samples
38 .. flat-table::
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| D | pixfmt-tch-td16.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _V4L2-TCH-FMT-DELTA-TD16:
11 16-bit signed little endian Touch Delta
19 Delta values may range from -32768 to 32767. Typically the values will vary
27 .. flat-table::
28 :header-rows: 0
29 :stub-columns: 0
32 * - start + 0:
33 - D'\ :sub:`00low`
34 - D'\ :sub:`00high`
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| D | pixfmt-srggb12p.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _V4L2-PIX-FMT-SRGGB12P:
4 .. _v4l2-pix-fmt-sbggr12p:
5 .. _v4l2-pix-fmt-sgbrg12p:
6 .. _v4l2-pix-fmt-sgrbg12p:
13 12-bit packed Bayer formats
14 ---------------------------
20 These four pixel formats are packed raw sRGB / Bayer formats with 12
26 Each n-pixel row contains n/2 green samples and n/2 blue or red
27 samples, with alternating green-red and green-blue rows. They are
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| D | pixfmt-tch-tu08.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _V4L2-TCH-FMT-TU08:
11 8-bit unsigned raw touch data
16 This format represents unsigned 8-bit data from a touch controller.
26 .. flat-table::
27 :header-rows: 0
28 :stub-columns: 0
31 * - start + 0:
32 - R'\ :sub:`00`
33 - R'\ :sub:`01`
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| /Documentation/hwmon/ |
| D | ucd9000.rst | 11 Addresses scanned: -
15 - http://focus.ti.com/lit/ds/symlink/ucd90120.pdf
16 - http://focus.ti.com/lit/ds/symlink/ucd90124.pdf
17 - http://focus.ti.com/lit/ds/symlink/ucd90160.pdf
18 - http://focus.ti.com/lit/ds/symlink/ucd90320.pdf
19 - http://focus.ti.com/lit/ds/symlink/ucd9090.pdf
20 - http://focus.ti.com/lit/ds/symlink/ucd90910.pdf
22 Author: Guenter Roeck <linux@roeck-us.net>
26 -----------
31 sequences up to 12 independent voltage rails. The device integrates a 12-bit
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| D | w83795.rst | 10 Addresses scanned: I2C 0x2c - 0x2f
18 Addresses scanned: I2C 0x2c - 0x2f
23 - Wei Song (Nuvoton)
24 - Jean Delvare <jdelvare@suse.de>
28 -----------
35 - W83795G
40 13 VSEN1 (VCORE1) 10h in0
42 15 VSEN3 (VCORE3) 12h in2
43 16 VSEN4 13h in3
60 11/ 12 VDSEN17/TR4/TD4 24h in20/temp4
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| /Documentation/admin-guide/pm/ |
| D | intel-speed-select.rst | 1 .. SPDX-License-Identifier: GPL-2.0
14 - https://www.intel.com/content/www/us/en/architecture-and-technology/speed-select-technology-artic…
15 - https://builders.intel.com/docs/networkbuilders/intel-speed-select-technology-base-frequency-enha…
19 dynamically without pre-configuring via BIOS setup options. This dynamic
29 intel-speed-select configuration tool
32 Most Linux distribution packages may include the "intel-speed-select" tool. If not,
38 # cd tools/power/x86/intel-speed-select/
43 ------------
47 # intel-speed-select --help
49 The top-level help describes arguments and features. Notice that there is a
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| /Documentation/devicetree/bindings/input/ |
| D | nvidia,tegra20-kbc.txt | 7 - compatible: "nvidia,tegra20-kbc"
8 - reg: Register base address of KBC.
9 - interrupts: Interrupt number for the KBC.
10 - nvidia,kbc-row-pins: The KBC pins which are configured as row. This is an
12 - nvidia,kbc-col-pins: The KBC pins which are configured as column. This is an
14 - linux,keymap: The keymap for keys as described in the binding document
15 devicetree/bindings/input/matrix-keymap.txt.
16 - clocks: Must contain one entry, for the module clock.
17 See ../clocks/clock-bindings.txt for details.
18 - resets: Must contain an entry for each entry in reset-names.
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| /Documentation/devicetree/bindings/leds/ |
| D | leds-pca955x.txt | 1 * NXP - pca955x LED driver
5 be input or output, and output pins can also be pulse-width controlled.
8 - compatible : should be one of :
14 - #address-cells: must be 1
15 - #size-cells: must be 0
16 - reg: I2C slave address. depends on the model.
19 - gpio-controller: allows pins to be used as GPIOs.
20 - #gpio-cells: must be 2.
21 - gpio-line-names: define the names of the GPIO lines
23 LED sub-node properties:
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| /Documentation/devicetree/bindings/clock/ |
| D | armada3700-periph-clock.txt | 14 -----------------------------------
27 12 ddr_fclk DDR F clock
28 13 trace Trace
35 -----------------------------------
36 0 gbe-50 50 MHz parent clock for Gigabit Ethernet
37 1 gbe-core parent clock for Gigabit Ethernet core
38 2 gbe-125 125 MHz parent clock for Gigabit Ethernet
39 3 gbe1-50 50 MHz clock for Gigabit Ethernet port 1
40 4 gbe0-50 50 MHz clock for Gigabit Ethernet port 0
41 5 gbe1-125 125 MHz clock for Gigabit Ethernet port 1
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| /Documentation/networking/ |
| D | multi-pf-netdev.rst | 1 .. SPDX-License-Identifier: GPL-2.0
5 Multi-PF Netdev
11 - `Background`_
12 - `Overview`_
13 - `mlx5 implementation`_
14 - `Channels distribution`_
15 - `Observability`_
16 - `Steering`_
17 - `Mutually exclusive features`_
22 The Multi-PF NIC technology enables several CPUs within a multi-socket server to connect directly to
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| /Documentation/devicetree/bindings/pinctrl/ |
| D | marvell,orion-pinctrl.txt | 3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,88f5181-pinctrl",
8 "marvell,88f5181l-pinctrl",
9 "marvell,88f5182-pinctrl",
10 "marvell,88f5281-pinctrl"
12 - reg: two register areas, the first one describing the first two
26 mpp2 2 gpio, pci(req3), pci-1(pme)
30 mpp6 6 gpio, pci(req5), pci-1(clk)
31 mpp7 7 gpio, pci(gnt5), pci-1(clk)
36 mpp12 12 gpio, ge(txd4)
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| /Documentation/devicetree/bindings/soc/qcom/ |
| D | qcom,apr-services.yaml | 1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/soc/qcom/qcom,apr-services.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
19 maximum: 13
31 12 = Ultrasound stream manager.
32 13 = Listen stream manager.
39 qcom,protection-domain:
40 $ref: /schemas/types.yaml#/definitions/string-array
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| /Documentation/networking/device_drivers/ethernet/smsc/ |
| D | smc9.rst | 1 .. SPDX-License-Identifier: GPL-2.0
20 1. The driver should work on all kernels from 1.2.13 until 1.3.71.
43 ftp://fenris.campus.vt.edu/smc9/smc9-12.tar.gz
44 ftp://sfbox.vt.edu/filebox/F/fenris/smc9/smc9-12.tar.gz
|
| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | brcm,bcm2835-armctrl-ic.txt | 1 BCM2835 Top-Level ("ARMCTRL") Interrupt Controller
3 The BCM2835 contains a custom top-level interrupt controller, which supports
4 72 interrupt sources using a 2-level register scheme. The interrupt
9 interrupts, but the per-CPU interrupt controller is the root, and an
14 - compatible : should be "brcm,bcm2835-armctrl-ic" or
15 "brcm,bcm2836-armctrl-ic"
16 - reg : Specifies base physical address and size of the registers.
17 - interrupt-controller : Identifies the node as an interrupt controller
18 - #interrupt-cells : Specifies the number of cells needed to encode an
28 Additional required properties for brcm,bcm2836-armctrl-ic:
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