Searched +full:125 +full:mhz (Results 1 – 21 of 21) sorted by relevance
| /Documentation/devicetree/bindings/clock/ |
| D | armada3700-periph-clock.txt | 36 0 gbe-50 50 MHz parent clock for Gigabit Ethernet
38 2 gbe-125 125 MHz parent clock for Gigabit Ethernet
39 3 gbe1-50 50 MHz clock for Gigabit Ethernet port 1
40 4 gbe0-50 50 MHz clock for Gigabit Ethernet port 0
41 5 gbe1-125 125 MHz clock for Gigabit Ethernet port 1
42 6 gbe0-125 125 MHz clock for Gigabit Ethernet port 0
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| D | starfive,jh7100-clkgen.yaml | 22 - description: Main clock source (25 MHz)
23 - description: Application-specific clock source (12-27 MHz)
24 - description: RMII reference clock (50 MHz)
25 - description: RGMII RX clock (125 MHz)
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| D | allwinner,sun7i-a20-gmac-clk.yaml | 26 The parent clocks shall be fixed rate dummy clocks at 25 MHz and
27 125 MHz, respectively.
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| D | starfive,jh7110-stgcrg.yaml | 21 - description: Main Oscillator (24 MHz)
24 - description: USB (125 MHz)
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| /Documentation/devicetree/bindings/net/ |
| D | adi,adin.yaml | 42 A 25MHz reference and a free-running 125MHz.
44 the 125MHz clocks based on its internal state.
47 - 25mhz-reference
48 - 125mhz-free-running
52 description: Enable 25MHz reference clock output on CLK25_REF pin.
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| D | rockchip-dwmac.yaml | 79 For RGMII, it must be "input", means main clock(125MHz)
81 For RMII, "input" means PHY provides the reference clock(50MHz),
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| /Documentation/devicetree/bindings/net/dsa/ |
| D | microchip,ksz.yaml | 45 microchip,synclko-125:
48 Set if the output SYNCLKO frequency should be set to 125MHz instead of 25MHz.
54 microchip,synclko-125.
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| /Documentation/devicetree/bindings/usb/ |
| D | dwc3-xilinx.yaml | 39 - description: Master/Core clock, has to be >= 125 MHz
40 for SS operation and >= 60MHz for HS operation.
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| D | qcom,dwc3.yaml | 81 - core:: Master/Core clock, has to be >= 125 MHz for SS operation and >=
82 60MHz for HS operation.
87 mode. Its frequency should be 19.2MHz.
189 - description: Master/Core clock, has to be >= 125 MHz
190 for SS operation and >= 60MHz for HS operation.
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| /Documentation/fb/ |
| D | viafb.modes | 10 # 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock)
29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
35 # 640x480, 75 Hz, Non-Interlaced (31.50 MHz dotclock)
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
56 # 640x480, 85 Hz, Non-Interlaced (36.000 MHz dotclock)
74 # D: 36.000 MHz, H: 43.269 kHz, V: 85.00 Hz
77 # 640x480, 100 Hz, Non-Interlaced (43.163 MHz dotclock)
95 # D: 43.163 MHz, H: 50.900 kHz, V: 100.00 Hz
98 # 640x480, 120 Hz, Non-Interlaced (52.406 MHz dotclock)
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| /Documentation/devicetree/bindings/input/ |
| D | iqs626a.yaml | 283 0: 4 MHz (1 MHz)
284 1: 2 MHz (500 kHz)
285 2: 1 MHz (250 kHz)
286 3: 500 kHz (125 kHz)
397 0: 16 MHz (4 MHz)
398 1: 8 MHz (2 MHz)
399 2: 4 MHz (1 MHz)
400 3: 2 MHz (500 kHz)
603 0: 4 MHz (1 MHz)
604 1: 2 MHz (500 kHz)
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| D | iqs269a.yaml | 180 0: 16 MHz (4 MHz)
181 1: 8 MHz (2 MHz)
182 2: 4 MHz (1 MHz)
183 3: 2 MHz (500 kHz)
389 0: 4 MHz (1 MHz)
390 1: 2 MHz (500 kHz)
391 2: 1 MHz (250 kHz)
392 3: 500 kHz (125 kHz)
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| /Documentation/admin-guide/pm/ |
| D | intel-speed-select.rst | 154 base-frequency(MHz):2600
168 condition is met, then base frequency of 2600 MHz can be maintained. To
183 base-frequency(MHz):2800
211 This matches the base-frequency (MHz) field value displayed from the
261 Which shows that the base frequency now increased from 2600 MHz at performance
262 level 0 to 2800 MHz at performance level 4. As a result, any workload, which can
263 use fewer CPUs, can see a boost of 200 MHz compared to performance level 0.
424 Specify clos min in MHz with [--min|-n]
425 Specify clos max in MHz with [--max|-m]
434 clos min is not specified, default: 0 MHz
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| /Documentation/networking/device_drivers/ethernet/chelsio/ |
| D | cxgb.rst | 188 Example for RTT with 100us: RX_WINDOW = (1,250,000 * 0.1) = 125,000
221 eth#: Chelsio N210 1x10GBaseX NIC (rev #), PCIX 133MHz/64-bit
307 chipset, you may experience the "133-Mhz Mode Split Completion Data
308 Corruption" bug identified by AMD while using a 133Mhz PCI-X card on the
313 is operating at 133 Mhz", causing data corruption.
318 For 133Mhz secondary bus operation, limit the transaction length and
327 section 56, "133-MHz Mode Split Completion Data Corruption" for more
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| /Documentation/networking/dsa/ |
| D | sja1105.rst | 332 In the RMII spec, the 50 MHz clock signals are either driven by the MAC or by
336 the 50 MHz clock themselves, in an attempt to be helpful.
370 In RGMII the clock frequency changes with link speed (125 MHz at 1000 Mbps, 25
371 MHz at 100 Mbps and 2.5 MHz at 10 Mbps), and link speed might change during the
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| /Documentation/networking/ |
| D | phy.rst | 73 electrical signal interface using a synchronous 125Mhz clock signal and several
241 This is serial MII, clocked at 125MHz, supporting 100M and 10M speeds.
308 rate of 125Mpbs using a 4B/5B encoding scheme, resulting in an underlying
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| D | can.rst | 1149 @133MHz with four SJA1000 CAN controllers from 2002 under heavy bus
1280 tq 125 prop-seg 6 phase-seg1 7 phase-seg2 2 sjw 1
1314 "tq 125 prop-seg 6 phase-seg1 7 phase-seg2 2 sjw 1"
1343 $ ip link set canX type can tq 125 prop-seg 6 \
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| /Documentation/userspace-api/media/v4l/ |
| D | vidioc-g-dv-timings.rst | 116 - Pixel clock in Hz. Ex. 74.25MHz->74250000
298 - Some formats like SMPTE-125M have an interlaced signal with a odd
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| /Documentation/admin-guide/media/ |
| D | bttv-cardlist.rst | 517 * - 125
670 - Bt848 Capture 14MHz
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| /Documentation/virt/kvm/x86/ |
| D | timekeeping.rst | 45 or PIT. The PIT has a fixed frequency 1.193182 MHz base clock and three
61 | 1.1932 MHz|---------->| CLOCK OUT | ---------> IRQ 0
232 000 = 4.194 MHz
233 001 = 1.049 MHz
245 1101 = 125 mS
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| /Documentation/scsi/ |
| D | ncr53c8xx.rst | 204 .. [1] Chip supports 33MHz and 66MHz PCI buses.
648 This option allows you to specify the frequency in MHz the driver
1623 The first table corresponds to Ultra chips 53875 and 53C860 with 80 MHz
1625 The second one has been calculated by setting the scsi clock to 40 Mhz
1678 |29 |116 | 8.620 |125 | 8.000 | |
1680 |30 |120 | 8.333 |125 | 8.000 | |
1682 |31 |124 | 8.064 |125 | 8.000 | |
1730 |26 |104 |9.615 |125 | 8.000 |
1732 |27 |108 |9.259 |125 | 8.000 |
1734 |28 |112 |8.928 |125 | 8.000 |
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