| /Documentation/admin-guide/ |
| D | highuid.rst | 2 Notes on the change from 16-bit UIDs to 32-bit UIDs
15 What's left to be done for 32-bit UIDs on all Linux architectures:
22 properly with huge UIDs. If it can deal with 64-bit file offsets on all
27 (currently, the old 16-bit UID and GID are still written to disk, and
28 part of the former pad space is used to store separate 32-bit UID and
31 - Need to validate that OS emulation calls the 16-bit UID
32 compatibility syscalls, if the OS being emulated used 16-bit UIDs, or
33 uses the 32-bit UID system calls properly otherwise.
40 (need to support whatever new 32-bit UID system calls are added to
45 At present, 32-bit UIDs _should_ work for:
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| /Documentation/devicetree/bindings/media/i2c/ |
| D | tda1997x.txt | 6 - RGB 8bit per color (24 bits total): R[11:4] B[11:4] G[11:4]
7 - YUV444 8bit per color (24 bits total): Y[11:4] Cr[11:4] Cb[11:4]
8 - YUV422 semi-planar 8bit per component (16 bits total): Y[11:4] CbCr[11:4]
9 - YUV422 semi-planar 10bit per component (20 bits total): Y[11:2] CbCr[11:2]
10 - YUV422 semi-planar 12bit per component (24 bits total): - Y[11:0] CbCr[11:0]
11 - YUV422 BT656 8bit per component (8 bits total): YCbCr[11:4] (2-cycles)
12 - YUV422 BT656 10bit per component (10 bits total): YCbCr[11:2] (2-cycles)
13 - YUV422 BT656 12bit per component (12 bits total): YCbCr[11:0] (2-cycles)
16 - RGB 12bit per color (36 bits total): R[11:0] B[11:0] G[11:0]
17 - YUV444 12bit per color (36 bits total): Y[11:0] Cb[11:0] Cr[11:0]
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| /Documentation/userspace-api/media/rc/ |
| D | rc-protos.rst | 17 Other things can be encoded too. Some IR protocols encode a toggle bit; this
20 toggle bit will invert from one IR message to the next.
41 * - rc-5 bit
43 - scancode bit
51 - Start bit, always set
57 - 2nd start bit in rc5, re-used as 6th command bit
63 - Toggle bit
78 where there the second stop bit is the 6th command bit, but inverted.
80 schemes. This bit is stored in bit 6 of the scancode, inverted. This is
85 This is much like rc-5 but one bit longer. The scancode is encoded
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| /Documentation/misc-devices/ |
| D | isl29003.rst | 21 The ISL29003 is an integrated light sensor with a 16-bit integrating type
24 provides 16-bit resolution while rejecting 50Hz and 60Hz flicker caused by
27 The driver allows to set the lux range, the bit resolution, the operational
48 2: 0 lux to 16,000 lux
54 0: 2^16 cycles (default)
62 0: diode1's current (unsigned 16bit) (default)
63 1: diode1's current (unsigned 16bit)
64 2: difference between diodes (l1 - l2, signed 15bit)
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| D | oxsemi-tornado.rst | 12 value from 1 to 63.875 in increments of 0.125, and then the usual 16-bit
15 that can take any value from 4 to 16 to divide the frequency further and
19 By default the oversampling rate is set to 16 and the clock prescaler is
21 for the usual 16-bit divisor is 115313.653, which is close enough to the
30 setting bit 4 of the EFR. In that mode setting bit 7 in the MCR enables
34 devices that do not have the extra prescaler's 9th bit in CPR2, so the
38 obtained, with either exact or highly-accurate actual bit rates for
61 r: 1843200, a: 1838235.29, d: -0.2694%, tcr: 16, cpr: 2.125, div: 1
64 r: 921600, a: 919117.65, d: -0.2694%, tcr: 16, cpr: 2.125, div: 2
77 r: 200, a: 200.00, d: 0.0000%, tcr: 16, cpr: 1.250, div: 15625
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| /Documentation/devicetree/bindings/gpio/ |
| D | gpio-74xx-mmio.txt | 5 "ti,741g125": for 741G125 (1-bit Input),
6 "ti,741g174": for 741G74 (1-bit Output),
7 "ti,742g125": for 742G125 (2-bit Input),
8 "ti,7474" : for 7474 (2-bit Output),
9 "ti,74125" : for 74125 (4-bit Input),
10 "ti,74175" : for 74175 (4-bit Output),
11 "ti,74365" : for 74365 (6-bit Input),
12 "ti,74174" : for 74174 (6-bit Output),
13 "ti,74244" : for 74244 (8-bit Input),
14 "ti,74273" : for 74273 (8-bit Output),
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| /Documentation/userspace-api/media/v4l/ |
| D | pixfmt-sdr-pcu16be.rst | 9 Planar complex unsigned 16-bit big endian IQ sample
16 and Q are represented as a 16 bit unsigned big endian number stored in
17 32 bit space. The remaining unused bits within the 32 bit space will be
20 the 16 bits, bit 15:2 (14 bit) is data and bit 1:0 (2 bit) can be any
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| D | pixfmt-inzi.rst | 9 Infrared 10-bit linked with Depth 16-bit images
24 Each pixel is 16-bit cell, with actual data stored in the 10 LSBs
29 The second plane provides 16-bit per-pixel Depth data arranged in
34 Each cell is a 16-bit word with more significant data stored at higher
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| D | pixfmt-z16.rst | 10 16-bit depth data with distance values at each pixel
16 This is a 16-bit format, representing depth data. Each pixel is a
19 is stored in a 16-bit word in the little endian byte order.
49 * - start + 16:
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| /Documentation/networking/device_drivers/cellular/qualcomm/ |
| D | rmnet.rst | 36 Bit 0 1 2-7 8-15 16-31
39 Bit 32-x
42 Command (1)/ Data (0) bit value is to indicate if the packet is a MAP command
62 Bit 0 1 2-7 8-15 16-31
65 Bit 32-(x-33) (x-32)-x
68 Command (1)/ Data (0) bit value is to indicate if the packet is a MAP command
87 Bit 0-14 15 16-31
90 Bit 31-47 48-64
95 Valid bit indicates whether the partial checksum is calculated and is valid.
115 Bit 0 1 2-7 8-15 16-31
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| /Documentation/scsi/ |
| D | NinjaSCSI.rst | 20 I-O data CBSC-II in 16 bit mode (NinjaSCSI-32Bi)
96 card "WorkBit NinjaSCSI-32Bi (16bit)"
97 version "WORKBIT", "UltraNinja-16", "1"
101 card "WorkBit NinjaSCSI-32Bi (16bit) / IO-DATA"
106 card "WorkBit NinjaSCSI-32Bi (16bit) / KME-1"
109 card "WorkBit NinjaSCSI-32Bi (16bit) / KME-2"
112 card "WorkBit NinjaSCSI-32Bi (16bit) / KME-3"
115 card "WorkBit NinjaSCSI-32Bi (16bit) / KME-4"
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| D | aic7xxx.rst | 26 aic7770 10 EISA/VL 10MHz 16Bit 4 1
27 aic7850 10 PCI/32 10MHz 8Bit 3
28 aic7855 10 PCI/32 10MHz 8Bit 3
29 aic7856 10 PCI/32 10MHz 8Bit 3
30 aic7859 10 PCI/32 20MHz 8Bit 3
31 aic7860 10 PCI/32 20MHz 8Bit 3
32 aic7870 10 PCI/32 10MHz 16Bit 16
33 aic7880 10 PCI/32 20MHz 16Bit 16
34 aic7890 20 PCI/32 40MHz 16Bit 16 3 4 5 6 7 8
35 aic7891 20 PCI/64 40MHz 16Bit 16 3 4 5 6 7 8
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| /Documentation/devicetree/bindings/display/ |
| D | simple-framebuffer.yaml | 97 * `a1r5g5b5` - 16-bit pixels, d[15]=a, d[14:10]=r, d[9:5]=g, d[4:0]=b
98 * `a2r10g10b10` - 32-bit pixels, d[31:30]=a, d[29:20]=r, d[19:10]=g, d[9:0]=b
99 * `a8b8g8r8` - 32-bit pixels, d[31:24]=a, d[23:16]=b, d[15:8]=g, d[7:0]=r
100 * `a8r8g8b8` - 32-bit pixels, d[31:24]=a, d[23:16]=r, d[15:8]=g, d[7:0]=b
101 * `r5g6b5` - 16-bit pixels, d[15:11]=r, d[10:5]=g, d[4:0]=b
102 * `r5g5b5a1` - 16-bit pixels, d[15:11]=r, d[10:6]=g, d[5:1]=b d[1:0]=a
103 * `r8g8b8` - 24-bit pixels, d[23:16]=r, d[15:8]=g, d[7:0]=b
104 * `x1r5g5b5` - 16-bit pixels, d[14:10]=r, d[9:5]=g, d[4:0]=b
105 * `x2r10g10b10` - 32-bit pixels, d[29:20]=r, d[19:10]=g, d[9:0]=b
106 * `x8r8g8b8` - 32-bit pixels, d[23:16]=r, d[15:8]=g, d[7:0]=b
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| /Documentation/devicetree/bindings/media/ |
| D | ti,da850-vpif.txt | 18 VPIF has a 16-bit parallel bus input, supporting 2 8-bit channels or a
19 single 16-bit channel. It should contain one or two port child nodes
25 Example using 2 8-bit input channels, one of which is connected to an
94 16-bit input (e.g. for raw-capture mode):
103 bus-width = <16>;
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| /Documentation/devicetree/bindings/dma/stm32/ |
| D | st,stm32-mdma.yaml | 21 3. A 32bit mask specifying the DMA channel configuration
22 -bit 0-1: Source increment mode
26 -bit 2-3: Destination increment mode
30 -bit 8-9: Source increment offset size
31 0x0: byte (8bit)
32 0x1: half-word (16bit)
33 0x2: word (32bit)
34 0x3: double-word (64bit)
35 -bit 10-11: Destination increment offset size
36 0x0: byte (8bit)
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| /Documentation/filesystems/ext4/ |
| D | blocks.rst | 12 pages). By default a filesystem can contain 2^32 blocks; if the '64bit'
17 For 32-bit filesystems, limits are as follows:
41 - 16TiB
45 - 16,384
50 - 16,384
64 - 16,843,020
71 - 16TiB
74 - 16GiB
79 For 64-bit filesystems, limits are as follows:
101 - 16ZiB
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| /Documentation/devicetree/bindings/input/ |
| D | pxa27x-keypad.txt | 8 recognized when it is pressed. It is a u32 value, and bit[31:16]
9 is debounce interval for direct key and bit[15:0] is debounce
18 are used. If bit[X] of the mask is set, the direct key X
28 - marvell,rotary0 : It is a u32 value. Bit[31:16] is the
29 linux key-code for rotary up. Bit[15:0] is the linux key-code
34 axes measurement in the device. It is a u32 value. Bit[31:16]
35 is for rotary 1, and Bit[15:0] is for rotary 0.
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| /Documentation/ABI/testing/ |
| D | configfs-usb-gadget-midi2 | 27 manufacturer Manufacture ID (24 bit)
28 family Device family ID (16 bit)
29 model Device model ID (16 bit)
30 sw_revision Software Revision (32 bit)
46 num_groups The number of groups in this FB (1-16)
48 midi1_num_groups The number of groups for MIDI 1.0 (0-16)
50 midi_ci_verison Supported MIDI-CI version number (8 bit)
52 sysex8_streams Max number of SysEx8 streams (8 bit)
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| D | devlink-resource-mlxsw | 3 KernelVersion: v4.16
15 KernelVersion: v4.16
22 KernelVersion: v4.16
26 64bit.
30 KernelVersion: v4.16
33 device. Used in case the key is larger than 64 bit.
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| /Documentation/core-api/ |
| D | dma-isa-lpc.rst | 37 The DMA-able address space is the lowest 16 MB of _physical_ memory.
46 __GFP_RETRY_MAYFAIL and __GFP_NOWARN to make the allocator try a bit harder.
69 8-bit transfers and the upper four are for 16-bit transfers.
73 This means that of the four 16-bits channels only three are usable.)
80 The ability to use 16-bit or 8-bit transfers is _not_ up to you as a
105 be 16-bit aligned for 16-bit transfers) and how many bytes to
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| D | packing.rst | 15 definitions from the hardware documentation into bit field indices for the
18 (sometimes even 64 bit ones). This creates the inconvenience of having to
24 high-level idea might get lost among the many bit shifts required.
25 Many drivers take the bit-shifting approach and then attempt to reduce the
44 perspective, bit 63 always means bit offset 7 of byte 7, albeit only
45 logically. The question is: where do we lay this bit out in memory?
57 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
63 bit i corresponds to the number 2^i. This is also referred to in the code
73 24 25 26 27 28 29 30 31 16 17 18 19 20 21 22 23 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7
77 inverts bit offsets inside a byte.
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| /Documentation/devicetree/bindings/iio/adc/ |
| D | maxim,max1027.yaml | 19 # 10-bit 8 channels
21 # 10-bit 12 channels
23 # 10-bit 16 channels
25 # 12-bit 8 channels
27 # 12-bit 12 channels
29 # 12-bit 16 channels
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| /Documentation/fb/ |
| D | arkfb.rst | 19 * 4 bpp pseudocolor modes (with 18bit palette, two variants)
20 * 8 bpp pseudocolor mode (with 18bit palette)
21 * 16 bpp truecolor modes (RGB 555 and RGB 565)
31 hardware). This limitation is not enforced by driver. Text mode supports 8bit
32 wide fonts only (hardware limitation) and 16bit tall fonts (driver
39 8bit wide fonts only (driver limitation).
55 * support for fontheight != 16 in text mode
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| D | vt8623fb.rst | 18 * 4 bpp pseudocolor modes (with 18bit palette, two variants)
19 * 8 bpp pseudocolor mode (with 18bit palette)
20 * 16 bpp truecolor mode (RGB 565)
30 driver. Text mode supports 8bit wide fonts only (hardware limitation) and
31 16bit tall fonts (driver limitation).
36 8bit wide fonts only (driver limitation).
50 * support for fontheight != 16 in text mode
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| /Documentation/devicetree/bindings/pwm/ |
| D | microchip,corepwm.yaml | 14 corePWM is an 16 channel pulse width modulator FPGA IP
42 A 16 bit wide "SHADOW_REG_EN" parameter of the IP core controls whether synchronous
46 At runtime a bit wide register exposed to APB can be used to toggle on/off
48 Each bit of "microchip,sync-update-mask" corresponds to a PWM channel & represents
59 standard PWM algorithm can achieve. A 16 bit DAC_MODE module parameter of the IP
62 Each bit corresponds to a PWM channel & represents whether DAC mode is enabled
|