Searched +full:1 +full:hz (Results 1 – 25 of 281) sorted by relevance
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| /Documentation/fb/ |
| D | viafb.modes | 10 # 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock)
14 # Scan Frequency 31.469 kHz 59.94 Hz
29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
33 geometry 480 640 480 640 32 timings 39722 72 24 19 1 48 3 endmode
35 # 640x480, 75 Hz, Non-Interlaced (31.50 MHz dotclock)
39 # Scan Frequency 37.500 kHz 75.00 Hz
43 # 2 chars 1 lines
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
54 geometry 640 480 640 480 32 timings 31747 120 16 16 1 64 3 endmode
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| D | viafb.rst | 21 640x480(60, 75, 85, 100, 120 Hz), 720x480(60 Hz),
22 720x576(60 Hz), 800x600(60, 75, 85, 100, 120 Hz),
23 848x480(60 Hz), 856x480(60 Hz), 1024x512(60 Hz),
24 1024x768(60, 75, 85, 100 Hz), 1152x864(75 Hz),
25 1280x768(60 Hz), 1280x960(60 Hz), 1280x1024(60, 75, 85 Hz),
26 1440x1050(60 Hz), 1600x1200(60, 75 Hz), 1280x720(60 Hz),
27 1920x1080(60 Hz), 1400x1050(60 Hz), 800x480(60 Hz)
44 viafb_SAMM_ON=1
60 - 1 : centering
64 1 : LCD panel with MSB data format input
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| /Documentation/ABI/testing/ |
| D | sysfs-bus-iio-adc-ad4130 | 8 1st conversion time. No natural 50/60Hz rejection.
10 * "sinc4+sinc1" - Sinc4 + averaging by 8. Low 1st conversion
13 * "sinc3" - Sinc3. Moderate 1st conversion time.
16 * "sinc3+rej60" - Sinc3 + 60Hz rejection. At a sampling
17 frequency of 50Hz, achieves simultaneous 50Hz and 60Hz
20 * "sinc3+sinc1" - Sinc3 + averaging by 8. Low 1st conversion
22 216.19Hz.
24 * "sinc3+pf1" - Sinc3 + Post Filter 1. 53dB rejection @
25 50Hz, 58dB rejection @ 60Hz.
28 50Hz, 70dB rejection @ 60Hz.
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| /Documentation/leds/ |
| D | leds-mlxcpld.rst | 57 - [0,1,0,1] = Red static ON
58 - [1,1,0,1] = Green static ON
59 - [0,1,1,0] = Red blink 3Hz
60 - [1,1,1,0] = Green blink 3Hz
61 - [0,1,1,1] = Red blink 6Hz
62 - [1,1,1,1] = Green blink 6Hz
102 - [0,1,0,1] = Red static ON
103 - [1,1,0,1] = Green static ON
104 - [0,1,1,0] = Red blink 3Hz
105 - [1,1,1,0] = Green blink 3Hz
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| /Documentation/devicetree/bindings/cpufreq/ |
| D | cpufreq-mediatek.txt | 34 Example 1 (MT7623 SoC):
41 opp-hz = /bits/ 64 <598000000>;
46 opp-hz = /bits/ 64 <747500000>;
51 opp-hz = /bits/ 64 <1040000000>;
56 opp-hz = /bits/ 64 <1196000000>;
61 opp-hz = /bits/ 64 <1300000000>;
76 cpu@1 {
101 opp-hz = /bits/ 64 <507000000>;
106 opp-hz = /bits/ 64 <702000000>;
111 opp-hz = /bits/ 64 <1001000000>;
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| /Documentation/devicetree/bindings/ufs/ |
| D | ufs-common.yaml | 18 freq-table-hz:
21 - description: Minimum frequency for given clock in Hz
22 - description: Maximum frequency for given clock in Hz
27 Array of <min max> operating frequencies in Hz stored in the same order
34 Preferred over freq-table-hz.
44 maxItems: 1
48 enum: [1, 2]
70 vcc-supply-1p8:
93 freq-table-hz: [ clocks ]
102 - freq-table-hz
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| /Documentation/input/devices/ |
| D | cma3000_d0x.rst | 26 axis and supports 400, 100, 40 Hz sample frequency.
42 event with value 1 when free fall is detected.
89 Event code 1 (Y)
102 Max 1
112 1: 100 Hz Measurement mode
113 2: 400 Hz Measurement mode
114 3: 40 Hz Measurement mode
116 5: 100 Hz Free fall mode
117 6: 40 Hz Free fall mode
133 (X & 0x0F) * 2.5 ms (FFTMR 400 Hz)
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| /Documentation/devicetree/bindings/iio/adc/ |
| D | atmel,sama5d2-adc.yaml | 20 maxItems: 1
23 maxItems: 1
26 maxItems: 1
34 atmel,min-sample-rate-hz:
37 atmel,max-sample-rate-hz:
50 enum: [1, 2, 3]
53 maxItems: 1
59 const: 1
71 - atmel,min-sample-rate-hz
72 - atmel,max-sample-rate-hz
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| D | adi,ad7192.yaml | 28 const: 1
34 maxItems: 1
41 maxItems: 1
59 maxItems: 1
75 adi,rejection-60-Hz-enable:
77 This bit enables a notch at 60 Hz when the first notch of the sinc
78 filter is at 50 Hz. When REJ60 is set, a filter notch is placed at
79 60 Hz when the sinc filter first notch is at 50 Hz. This allows
80 simultaneous 50 Hz/ 60 Hz rejection.
99 When this bit is set to 1, the 500 nA current sources in the signal
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| /Documentation/devicetree/bindings/hwmon/ |
| D | adt7475.yaml | 40 maxItems: 1
45 the pwm uses a logic low output for 100% duty cycle. If set to 1 the pwm
52 enum: [0, 1]
53 default: 1
60 - 1: The PWM period in nanoseconds
61 - 90909091 (11 Hz)
62 - 71428571 (14 Hz)
63 - 45454545 (22 Hz)
64 - 34482759 (29 Hz)
65 - 28571429 (35 Hz)
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| /Documentation/hwmon/ |
| D | adt7470.rst | 47 The ADT7470 has a 8-bit ADC and is capable of measuring temperatures with 1
78 * 11.0 Hz
79 * 14.7 Hz
80 * 22.1 Hz
81 * 29.4 Hz
82 * 35.3 Hz
83 * 44.1 Hz
84 * 58.8 Hz
85 * 88.2 Hz
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| /Documentation/devicetree/bindings/opp/ |
| D | opp-v2.yaml | 24 * Example 1: Single cluster Dual-core ARM cortex A9, switch DVFS states
28 #address-cells = <1>;
42 cpu@1 {
45 reg = <1>;
59 opp-hz = /bits/ 64 <1000000000>;
66 opp-hz = /bits/ 64 <1100000000>;
72 opp-hz = /bits/ 64 <1200000000>;
85 #address-cells = <1>;
99 cpu@1 {
102 reg = <1>;
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| D | allwinner,sun50i-h6-operating-points.yaml | 48 opp-hz: true
52 maxItems: 1
61 - opp-hz
76 opp-hz = /bits/ 64 <480000000>;
85 opp-hz = /bits/ 64 <1080000000>;
94 opp-hz = /bits/ 64 <1488000000>;
110 opp-hz = /bits/ 64 <480000000>;
118 opp-hz = /bits/ 64 <792000000>;
127 opp-hz = /bits/ 64 <1512000000>;
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| D | opp-v2-kryo-cpu.yaml | 48 opp-hz: true
59 1: MSM8996, speedbin 1
67 5: MSM8996SG, speedbin 1
73 1: IPQ8064/IPQ8066/IPQ8068
87 - opp-hz
135 CPU1: cpu@1 {
157 clocks = <&kryocc 1>;
177 clocks = <&kryocc 1>;
214 opp-hz = /bits/ 64 <307200000>;
221 opp-hz = /bits/ 64 <1401600000>;
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| /Documentation/scheduler/ |
| D | sched-nice-design.rst | 14 units were driven by the HZ tick, so the smallest timeslice was 1/HZ.
16 In the O(1) scheduler (in 2003) we changed negative nice levels to be
19 rule so that nice +19 level would be _exactly_ 1 jiffy. To better
44 HZ=1000 it caused 1 jiffy to be 1 msec, which meant 0.1% CPU usage which
51 So for HZ=1000 we changed nice +19 to 5msecs, because that felt like the
53 But the fundamental HZ-sensitive property for nice+19 still remained,
59 within the constraints of HZ and jiffies and their nasty design level
77 With the old scheduler, if you for example started a niced task with +1
91 enough), the scheduler was decoupled from 'time slice' and HZ concepts
94 support: with the new scheduler nice +19 tasks get a HZ-independent
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| /Documentation/devicetree/bindings/gpu/ |
| D | arm,mali-midgard.yaml | 57 maxItems: 1
72 minItems: 1
76 minItems: 1
86 maxItems: 1
89 minItems: 1
173 opp-hz = /bits/ 64 <533000000>;
177 opp-hz = /bits/ 64 <450000000>;
181 opp-hz = /bits/ 64 <400000000>;
185 opp-hz = /bits/ 64 <350000000>;
189 opp-hz = /bits/ 64 <266000000>;
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| /Documentation/devicetree/bindings/display/msm/ |
| D | qcom,x1e80100-mdss.yaml | 29 maxItems: 1
93 #interrupt-cells = <1>;
97 #address-cells = <1>;
98 #size-cells = <1>;
128 #address-cells = <1>;
138 port@1 {
139 reg = <1>;
150 opp-hz = /bits/ 64 <200000000>;
155 opp-hz = /bits/ 64 <325000000>;
160 opp-hz = /bits/ 64 <375000000>;
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| D | qcom,sm7150-mdss.yaml | 37 maxItems: 1
113 #interrupt-cells = <1>;
127 #address-cells = <1>;
128 #size-cells = <1>;
160 #address-cells = <1>;
170 port@1 {
171 reg = <1>;
189 opp-hz = /bits/ 64 <19200000>;
194 opp-hz = /bits/ 64 <200000000>;
199 opp-hz = /bits/ 64 <300000000>;
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| D | qcom,sc7280-mdss.yaml | 36 maxItems: 1
108 #address-cells = <1>;
109 #size-cells = <1>;
123 #interrupt-cells = <1>;
159 #address-cells = <1>;
169 port@1 {
170 reg = <1>;
208 assigned-clock-parents = <&mdss_dsi_phy 0>, <&mdss_dsi_phy 1>;
216 #address-cells = <1>;
220 #address-cells = <1>;
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| D | qcom,sm7150-dpu.yaml | 89 #address-cells = <1>;
99 port@1 {
100 reg = <1>;
118 opp-hz = /bits/ 64 <19200000>;
123 opp-hz = /bits/ 64 <200000000>;
128 opp-hz = /bits/ 64 <300000000>;
133 opp-hz = /bits/ 64 <344000000>;
138 opp-hz = /bits/ 64 <430000000>;
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| D | qcom,sm8450-dpu.yaml | 92 #address-cells = <1>;
102 port@1 {
103 reg = <1>;
114 opp-hz = /bits/ 64 <172000000>;
119 opp-hz = /bits/ 64 <200000000>;
124 opp-hz = /bits/ 64 <325000000>;
129 opp-hz = /bits/ 64 <375000000>;
134 opp-hz = /bits/ 64 <500000000>;
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| /Documentation/devicetree/bindings/memory-controllers/ |
| D | rockchip,rk3399-dmc.yaml | 24 maxItems: 1
42 maxItems: 1
116 Defines the PHY dll bypass frequency in MHz (Mega Hz). When DDR frequency
131 frequency in Hz. When the DDR frequency is less then ddr3_odt_dis_freq,
179 frequency in Hz. When DDR frequency is less then ddr3_odt_dis_freq, the
226 frequency in Hz. When the DDR frequency is less then ddr3_odt_dis_freq,
316 rockchip,pd-idle-dis-freq-hz:
318 Defines the power-down idle disable frequency in Hz. When the DDR
322 rockchip,sr-idle-dis-freq-hz:
324 Defines the self-refresh idle disable frequency in Hz. When the DDR
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| /Documentation/devicetree/bindings/input/ |
| D | pwm-beeper.yaml | 17 maxItems: 1
22 beeper-hz:
23 description: bell frequency in Hz
40 beeper-hz = <1000>;
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| /Documentation/devicetree/bindings/sound/ |
| D | cs42l56.txt | 32 1 = 0.6 x VA
41 1 = Fixed - Headphone and Line Amp supply = + or - VCP/2.
47 0 = 1.8Hz
48 1 = 119Hz
49 2 = 236Hz
50 3 = 464Hz
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| /Documentation/gpu/ |
| D | panfrost.rst | 27 drm-maxfreq-fragment: 799999987 Hz
28 drm-curfreq-fragment: 799999987 Hz
31 drm-maxfreq-vertex-tiler: 799999987 Hz
32 drm-curfreq-vertex-tiler: 799999987 Hz
49 Where `N` is either `0` or `1`, depending on the desired enablement status.
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