| /Documentation/userspace-api/media/dvb/ |
| D | fe-bandwidth-t.rst | 10 :header-rows: 1
14 - .. row 1
30 - .. _BANDWIDTH-1-712-MHZ:
34 - 1.712 MHz
38 - .. _BANDWIDTH-5-MHZ:
42 - 5 MHz
46 - .. _BANDWIDTH-6-MHZ:
50 - 6 MHz
54 - .. _BANDWIDTH-7-MHZ:
58 - 7 MHz
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| /Documentation/fb/ |
| D | viafb.modes | 10 # 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock)
29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
33 geometry 480 640 480 640 32 timings 39722 72 24 19 1 48 3 endmode
35 # 640x480, 75 Hz, Non-Interlaced (31.50 MHz dotclock)
43 # 2 chars 1 lines
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
54 geometry 640 480 640 480 32 timings 31747 120 16 16 1 64 3 endmode
56 # 640x480, 85 Hz, Non-Interlaced (36.000 MHz dotclock)
64 # 7 chars 1 lines
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| /Documentation/devicetree/bindings/mfd/ |
| D | omap-usb-host.txt | 16 from 1 to 3. If the port mode is not specified, that port is treated
33 ULPI bypass control bit. e.g. OMAP3 silicon <= ES2.1
40 * "usbhost_120m_fck" - 120MHz Functional clock.
43 * "refclk_60m_int" - 60MHz internal reference clock for UTMI clock mux
44 * "refclk_60m_ext_p1" - 60MHz external ref. clock for Port 1's UTMI clock mux.
45 * "refclk_60m_ext_p2" - 60MHz external ref. clock for Port 2's UTMI clock mux
46 * "utmi_p1_gfclk" - Port 1 UTMI clock mux.
48 * "usb_host_hs_utmi_p1_clk" - Port 1 UTMI clock gate.
51 * "usb_host_hs_hsic480m_p1_clk" - Port 1 480MHz HSIC clock gate.
52 * "usb_host_hs_hsic480m_p2_clk" - Port 2 480MHz HSIC clock gate.
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| /Documentation/devicetree/bindings/cpu/ |
| D | cpu-capacity.txt | 6 1 - Introduction
38 by the frequency (in MHz) at which the benchmark has been run, so that
39 DMIPS/MHz are obtained. Such values are then normalized w.r.t. the highest
43 3 - capacity-dmips-mhz
46 capacity-dmips-mhz is an optional cpu node [1] property: u32 value
47 representing CPU capacity expressed in normalized DMIPS/MHz. At boot time, the
51 capacity-dmips-mhz property is all-or-nothing: if it is specified for a cpu
55 mhz values (normalized w.r.t. the highest value found while parsing the DT).
61 Example 1 (ARM 64-bit, 6-cpu system, two clusters):
62 The capacities-dmips-mhz or DMIPS/MHz values (scaled to 1024)
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| /Documentation/devicetree/bindings/clock/ |
| D | maxim,max9485.txt | 5 - MAX9485_MCLKOUT: A gated, buffered output of the input clock of 27 MHz
8 - MAX9485_CLKOUT[1,2]: Two gated outputs for MAX9485_CLKOUT
10 MAX9485_CLKOUT[1,2] are children of MAX9485_CLKOUT which upchain all rate set
15 - clocks: Input clock, must provide 27.000 MHz
17 - #clock-cells: From common clock binding; shall be set to 1
34 xo-27mhz: xo-27mhz {
45 clocks = <&xo-27mhz>;
46 reset-gpios = <&gpio 1 GPIO_ACTIVE_HIGH>;
48 #clock-cells = <1>;
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| D | samsung,exynos850-clock.yaml | 20 two external clocks:: OSCCLK (26 MHz) and RTCCLK (32768 Hz). Those external
49 minItems: 1
53 minItems: 1
57 const: 1
60 maxItems: 1
73 - description: External reference clock (26 MHz)
89 - description: External reference clock (26 MHz)
107 - description: External reference clock (26 MHz)
125 - description: External reference clock (26 MHz)
143 - description: External reference clock (26 MHz)
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| D | armada3700-periph-clock.txt | 16 1 sata_host Sata Host
25 10 i2c_1 I2C 1
36 0 gbe-50 50 MHz parent clock for Gigabit Ethernet
37 1 gbe-core parent clock for Gigabit Ethernet core
38 2 gbe-125 125 MHz parent clock for Gigabit Ethernet
39 3 gbe1-50 50 MHz clock for Gigabit Ethernet port 1
40 4 gbe0-50 50 MHz clock for Gigabit Ethernet port 0
41 5 gbe1-125 125 MHz clock for Gigabit Ethernet port 1
42 6 gbe0-125 125 MHz clock for Gigabit Ethernet port 0
43 7 gbe1-core Gigabit Ethernet core port 1
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| D | samsung,exynosautov9-clock.yaml | 20 two external clocks:: OSCCLK/XTCXO (26 MHz) and RTCCLK/XrtcXTI (32768 Hz).
47 minItems: 1
51 minItems: 1
55 const: 1
58 maxItems: 1
71 - description: External reference clock (26 MHz)
87 - description: External reference clock (26 MHz)
105 - description: External reference clock (26 MHz)
123 - description: External reference clock (26 MHz)
141 - description: External reference clock (26 MHz)
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| D | tesla,fsd-clock.yaml | 16 The root clock comes from external OSC clock (24 MHz).
33 minItems: 1
37 minItems: 1
41 const: 1
44 maxItems: 1
56 - description: External reference clock (24 MHz)
70 - description: External reference clock (24 MHz)
90 - description: External reference clock (24 MHz)
114 - description: External reference clock (24 MHz)
134 - description: External reference clock (24 MHz)
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| D | starfive,jh7100-clkgen.yaml | 18 maxItems: 1
22 - description: Main clock source (25 MHz)
23 - description: Application-specific clock source (12-27 MHz)
24 - description: RMII reference clock (50 MHz)
25 - description: RGMII RX clock (125 MHz)
35 const: 1
55 #clock-cells = <1>;
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| D | sophgo,sg2042-pll.yaml | 17 maxItems: 1
21 - description: Oscillator(Clock Generation IC) for Main/Fixed PLL (25 MHz)
22 - description: Oscillator(Clock Generation IC) for DDR PLL 0 (25 MHz)
23 - description: Oscillator(Clock Generation IC) for DDR PLL 1 (25 MHz)
32 const: 1
52 #clock-cells = <1>;
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| D | samsung,exynosautov920-clock.yaml | 19 two external clocks:: OSCCLK/XTCXO (38.4 MHz) and RTCCLK/XrtcXTI (32768 Hz).
42 minItems: 1
46 minItems: 1
50 const: 1
53 maxItems: 1
66 - description: External reference clock (38.4 MHz)
84 - description: External reference clock (38.4 MHz)
105 - description: External reference clock (38.4 MHz)
123 - description: External reference clock (38.4 MHz)
152 #clock-cells = <1>;
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| D | google,gs101-clock.yaml | 16 is OSCCLK (24.576 MHz). That external clock must be defined as a fixed-rate
39 minItems: 1
43 minItems: 1
47 const: 1
50 maxItems: 1
71 - description: External reference clock (24.576 MHz)
87 - description: External reference clock (24.576 MHz)
112 - description: External reference clock (24.576 MHz)
156 - description: External reference clock (24.576 MHz)
157 - description: Connectivity Peripheral 0/1 bus clock (from CMU_TOP)
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| D | samsung,exynos7885-clock.yaml | 20 is an external clock: OSCCLK (26 MHz). This external clock must be defined
40 minItems: 1
44 minItems: 1
48 const: 1
51 maxItems: 1
64 - description: External reference clock (26 MHz)
80 - description: External reference clock (26 MHz)
102 - description: External reference clock (26 MHz)
128 - description: External reference clock (26 MHz)
169 #clock-cells = <1>;
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| /Documentation/devicetree/bindings/net/ |
| D | adi,adin.yaml | 42 A 25MHz reference and a free-running 125MHz.
44 the 125MHz clocks based on its internal state.
47 - 25mhz-reference
48 - 125mhz-free-running
52 description: Enable 25MHz reference clock output on CLK25_REF pin.
60 #address-cells = <1>;
74 #address-cells = <1>;
79 ethernet-phy@1 {
80 reg = <1>;
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| D | qcom,ipq4019-mdio.yaml | 27 const: 1
33 minItems: 1
42 - description: MDIO clock source frequency fixed to 100MHZ
53 MDC rate is feed by an external clock (fixed 100MHz) and is divider
57 To follow 802.3 standard that instruct up to 2.5MHz by default, if
59 default 1.5625Mhz is select.
95 #address-cells = <1>;
104 ethphy1: ethernet-phy@1 {
105 reg = <1>;
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| /Documentation/devicetree/bindings/media/i2c/ |
| D | sony,imx412.yaml | 27 maxItems: 1
34 description: Clock frequency 6MHz, 12MHz, 18MHz, 24MHz or 27MHz
35 maxItems: 1
48 maxItems: 1
81 #address-cells = <1>;
84 camera@1a {
96 data-lanes = <1 2 3 4>;
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| D | sony,imx415.yaml | 13 The Sony IMX415 is a diagonal 6.4 mm (Type 1/2.8) CMOS active pixel type
28 maxItems: 1
31 description: Input clock (24 MHz, 27 MHz, 37.125 MHz, 72 MHz or 74.25 MHz)
32 maxItems: 1
45 maxItems: 1
60 - const: 1
63 - const: 1
91 #address-cells = <1>;
94 imx415: camera-sensor@1a {
108 data-lanes = <1 2 3 4>;
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| /Documentation/admin-guide/pm/ |
| D | intel-speed-select.rst | 69 Platform: API version : 1
70 Platform: Driver version : 1
71 Platform: mbox supported : 1
72 Platform: mmio supported : 1
106 package-1
131 package-1
152 enable-cpu-list:0,1,2,3,4,5,6,7,8,9,10,11,12,13,28,29,30,31,32,33,34,35,36,37,38,39,40,41
154 base-frequency(MHz):2600
168 condition is met, then base frequency of 2600 MHz can be maintained. To
181 enable-cpu-list:0,1,2,3,5,7,8,9,10,11,28,29,30,31,33,35,36,37,38,39
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| /Documentation/scsi/ |
| D | dc395x.rst | 29 Default: 0, Acceptable values: 0 or 1
31 If safe is set to 1 then the adapter will use conservative
42 Default: 1, Acceptable value: 0 to 7
45 0 20 Mhz
46 1 12.2 Mhz
47 2 10 Mhz
48 3 8 Mhz
49 4 6.7 Mhz
51 6 5 Mhz
52 7 4 Mhz
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| /Documentation/userspace-api/media/drivers/ |
| D | max2175.rst | 17 :widths: 1 4
21 * - ``(1)``
31 :widths: 1 4
35 * - ``(1)``
48 :widths: 1 4
53 samples/sec with a 10.24 MHz sck.
54 * - ``"DAB 1.2" (1)``
56 samples/sec with a 32.768 MHz sck.
61 samples/sec with a 14.88375 MHz sck.
62 * - ``"DAB 1.2" (1)``
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| /Documentation/devicetree/bindings/regulator/ |
| D | mps,mpq7920.yaml | 14 pattern: "pmic@[0-9a-f]{1,2}"
20 maxItems: 1
27 after their hardware counterparts BUCK[1-4], one LDORTC, and LDO[2-5]
32 enum: [0, 1, 2, 3]
36 1.1MHz, 1.65MHz, 2.2MHz, 2.75MHz
44 "^ldo[1-4]$":
49 "^buck[1-4]$":
56 enum: [0, 1, 2, 3]
63 enum: [0, 1, 2, 3]
87 #address-cells = <1>;
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| D | maxim,max8952.yaml | 21 enum: [0, 1, 2, 3]
36 maxItems: 1
42 enum: [0, 1, 2, 3, 4, 5, 6, 7]
47 - 1: 16mV/us
51 - 5: 1mV/us
58 enum: [0, 1, 2]
62 - 0: 26 MHz
63 - 1: 13 MHz
64 - 2: 19.2 MHz
65 Defaults to 26 MHz if not specified.
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| /Documentation/devicetree/bindings/usb/ |
| D | rockchip,dwc3.yaml | 44 maxItems: 1
47 maxItems: 1
53 Controller reference clock, must to be 24 MHz
55 Controller suspend clock, must to be 24 MHz or 32 KHz
57 Master/Core clock, must to be >= 62.5 MHz for SS
58 operation and >= 30MHz for HS operation
76 maxItems: 1
79 maxItems: 1
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| /Documentation/admin-guide/media/ |
| D | dvb_intro.rst | 102 Table 1. Transponder Frequencies Mount Dandenong, Vic, Aus.
107 Seven 177.500 Mhz
108 SBS 184.500 Mhz
109 Nine 191.625 Mhz
110 Ten 219.500 Mhz
111 ABC 226.500 Mhz
112 Channel 31 557.625 Mhz
133 T 177500000 7MHz AUTO AUTO QAM64 8k 1/16 NONE
134 T 184500000 7MHz AUTO AUTO QAM64 8k 1/8 NONE
135 T 191625000 7MHz AUTO AUTO QAM64 8k 1/16 NONE
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