Searched +full:1 +full:a000 (Results 1 – 25 of 34) sorted by relevance
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| /Documentation/devicetree/bindings/hsi/ |
| D | omap-ssi.txt | 24 - #address-cells: Should be set to <1>
25 - #size-cells: Should be set to <1>
37 0 and 1 (in this order).
70 #address-cells = <1>;
71 #size-cells = <1>;
74 ssi-port@4805a000 {
89 ssi-port@4805a000 {
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| /Documentation/devicetree/bindings/ata/ |
| D | ata-generic.yaml | 29 enum: [ 1, 2 ]
32 maxItems: 1
52 compact-flash@1a000 {
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| /Documentation/devicetree/bindings/i2c/ |
| D | microchip,corei2c.yaml | 24 maxItems: 1
27 maxItems: 1
30 maxItems: 1
48 i2c@2010a000 {
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| /Documentation/devicetree/bindings/dma/ |
| D | nvidia,tegra20-apbdma.txt | 14 - #dma-cells : Must be <1>. This dictates the length of DMA specifiers in
21 apbdma: dma@6000a000 {
43 #dma-cells = <1>;
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| D | ti-dma-crossbar.txt | 27 dmas = <&edma_xbar 12 0 1>; where <12> is the DMA request number, <0> is the TC
28 the event should be assigned and <1> is the mux selection for in the crossbar.
41 #dma-cells = <1>;
50 #dma-cells = <1>;
59 uart1: serial@4806a000 {
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| /Documentation/devicetree/bindings/media/ |
| D | mediatek-jpeg-encoder.yaml | 25 maxItems: 1
28 maxItems: 1
31 maxItems: 1
38 maxItems: 1
65 jpegenc: jpegenc@1500a000 {
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| D | ti-am437x-vpfe.txt | 15 1 - 8 Bit BT656 Interface.
32 pinctrl-1 = <&vpfe_pins_sleep>;
35 #address-cells = <1>;
48 i2c1: i2c@4802a000 {
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| D | nvidia,tegra-vde.yaml | 44 maxItems: 1
64 maxItems: 1
77 maxItems: 1
95 video-codec@6001a000 {
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| /Documentation/devicetree/bindings/serial/ |
| D | fsl-mxs-auart.yaml | 26 maxItems: 1
29 maxItems: 1
45 minItems: 1
51 minItems: 1
87 auart0: serial@8006a000 {
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| /Documentation/devicetree/bindings/pinctrl/ |
| D | ti,iodelay.txt | 22 dra7_iodelay_core: padconf@4844a000 {
25 #address-cells = <1>;
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| D | brcm,iproc-gpio.txt | 33 bit[0]: polarity (0 for active high and 1 for active low)
49 1. Phandle of pin-controller.
73 gpio_ccm: gpio@1800a000 {
90 pins = "gpio-1";
104 gpio-ranges = <&pinctrl 0 42 1>,
105 <&pinctrl 1 44 3>;
109 * Touchscreen that uses the CCM GPIO 0 and 1
115 gpio-event = <&gpio_ccm 1 0>;
122 bcm,rfkill-bank-sel = <&gpio_asiu 5 1>
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| /Documentation/devicetree/bindings/pwm/ |
| D | nvidia,tegra20-pwm.yaml | 39 maxItems: 1
42 maxItems: 1
63 pinctrl-1:
88 pwm: pwm@7000a000 {
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| D | allwinner,sun4i-a10-pwm.yaml | 41 maxItems: 1
44 minItems: 1
50 minItems: 1
56 maxItems: 1
85 maxItems: 1
96 pwm: pwm@1c20e00 {
107 pwm@300a000 {
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| /Documentation/devicetree/bindings/gpio/ |
| D | rockchip,gpio-bank.yaml | 19 maxItems: 1
22 maxItems: 1
25 minItems: 1
67 #address-cells = <1>;
68 #size-cells = <1>;
71 gpio0: gpio@2000a000 {
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| /Documentation/devicetree/bindings/display/mediatek/ |
| D | mediatek,ufoe.yaml | 32 maxItems: 1
35 maxItems: 1
64 ufoe@1401a000 {
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| /Documentation/devicetree/bindings/soc/fsl/ |
| D | fsl,bman.yaml | 41 minItems: 1
76 bman@31a000 {
79 interrupts = <16 IRQ_TYPE_EDGE_FALLING 1 2>;
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| /Documentation/devicetree/bindings/phy/ |
| D | qcom,usb-hs-28nm.yaml | 21 maxItems: 1
75 usb2_phy_prim: phy@7a000 {
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| /Documentation/devicetree/bindings/clock/ti/davinci/ |
| D | pll.txt | 38 - #clock-cells: shall be 1
68 #clock-cells = <1>;
80 pll1: clock-controller@21a000 {
87 #clock-cells = <1>;
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| /Documentation/devicetree/bindings/display/msm/ |
| D | gmu.yaml | 27 - pattern: '^qcom,adreno-gmu-x[1-9][0-9][0-9]\.[0-9]$'
32 minItems: 1
36 minItems: 1
68 maxItems: 1
231 - qcom,adreno-gmu-x185.1
295 gmu: gmu@506a000 {
321 gmu_wrapper: gmu@596a000 {
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| /Documentation/devicetree/bindings/arm/mediatek/ |
| D | mediatek,mt7622-wed.yaml | 29 maxItems: 1
32 maxItems: 1
80 wed0: wed@1020a000 {
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| /Documentation/devicetree/bindings/spi/ |
| D | mediatek,spi-mt65xx.yaml | 53 maxItems: 1
56 maxItems: 1
76 minItems: 1
79 enum: [0, 1, 2, 3]
102 spi@1100a000 {
104 #address-cells = <1>;
113 mediatek,pad-select = <1>, <0>;
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| /Documentation/devicetree/bindings/net/ |
| D | qca,qca7000.txt | 40 #address-cells = <1>;
51 spi-cpha; /* SPI mode: CPHA=1 */
52 spi-cpol; /* SPI mode: CPOL=1 */
76 auart0: serial@8006a000 {
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| /Documentation/devicetree/bindings/net/can/ |
| D | nxp,sja1000.yaml | 25 maxItems: 1
28 maxItems: 1
31 maxItems: 1
34 maxItems: 1
38 default: 1
39 enum: [ 1, 2, 4 ]
50 enum: [ 0, 1, 2, 3 ]
51 default: 1
55 <1> : normal output mode (default)
116 can@1a000 {
[all …]
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| /Documentation/devicetree/bindings/watchdog/ |
| D | qcom-wdt.yaml | 58 maxItems: 1
61 maxItems: 1
78 minItems: 1
99 minItems: 1
134 watchdog@200a000 {
136 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,
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| /Documentation/devicetree/bindings/edac/ |
| D | apm-xgene-edac.txt | 45 - compatible : Shall be "apm,xgene-edac-soc-v1" for revision 1 or
66 efuse: efuse@1054a000 {
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