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/Documentation/devicetree/bindings/rtc/
Depson,rtc7301.yaml24 maxItems: 1
30 enum: [1, 4]
34 maxItems: 1
45 rtc: rtc@44a00000 {
/Documentation/devicetree/bindings/spi/
Dspi-sprd.txt14 address on the SPI bus. Should be set to 1.
23 spi0: spi@70a00000{
31 #address-cells = <1>;
Dadi,axi-spi-engine.yaml10 The AXI SPI Engine controller is part of the SPI Engine framework[1] and
15 [1] https://wiki.analog.com/resources/fpga/peripherals/spi_engine
29 maxItems: 1
32 maxItems: 1
55 spi@44a00000 {
62 #address-cells = <1>;
/Documentation/devicetree/bindings/iio/dac/
Dadi,axi-dac.yaml29 maxItems: 1
32 maxItems: 1
39 maxItems: 1
54 dac@44a00000 {
/Documentation/devicetree/bindings/iio/adc/
Dadi,axi-adc.yaml29 maxItems: 1
32 maxItems: 1
35 maxItems: 1
60 axi-adc@44a00000 {
/Documentation/devicetree/bindings/remoteproc/
Dqcom,glink-edge.yaml39 maxItems: 1
47 maxItems: 1
83 remoteproc@8a00000 {
Dqcom,sc7280-wpss-pil.yaml22 maxItems: 1
79 maxItems: 1
83 maxItems: 1
164 remoteproc@8a00000 {
170 <&wpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
/Documentation/devicetree/bindings/mtd/
Dingenic,nand.yaml29 minItems: 1
47 maxItems: 1
51 maxItems: 1
68 #size-cells = <1>;
69 ranges = <1 0 0x1b000000 0x1000000>,
78 nand-controller@1 {
80 reg = <1 0 0x1000000>;
82 #address-cells = <1>;
96 nand@1 {
97 reg = <1>;
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/Documentation/devicetree/bindings/serial/
Dsamsung_uart.yaml46 maxItems: 1
52 enum: [ 1, 4 ]
74 minItems: 1
78 maxItems: 1
197 serial_0: serial@10a00000 {
/Documentation/devicetree/bindings/display/msm/
Dqcom,mdss.yaml37 maxItems: 1
42 const: 1
45 maxItems: 1
57 - minItems: 1
70 - minItems: 1
76 const: 1
79 const: 1
102 "^display-controller@[1-9a-f][0-9a-f]*$":
110 "^dsi@[1-9a-f][0-9a-f]*$":
118 "^phy@[1-9a-f][0-9a-f]*$":
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Dhdmi.yaml25 minItems: 1
29 minItems: 1
33 minItems: 1
37 minItems: 1
44 maxItems: 1
47 maxItems: 1
66 maxItems: 1
70 maxItems: 1
75 maxItems: 1
80 maxItems: 1
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/Documentation/devicetree/bindings/display/bridge/
Dnwl-dsi.yaml25 maxItems: 1
28 maxItems: 1
31 const: 1
61 maxItems: 1
70 maxItems: 1
101 endpoint@1:
109 - endpoint@1
113 port@1:
121 - port@1
147 dsi@30a00000 {
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/Documentation/devicetree/bindings/display/ti/
Dti,am65x-dss.yaml17 supports 1 OLDI TX and in AM625 DSS, the first video port output is
38 - description: VP1 video port 1
56 - description: vp1 Video Port 1 pixel clock
66 minItems: 1
70 minItems: 1
74 maxItems: 1
77 maxItems: 1
90 For AM65x DSS, the OLDI output port node from video port 1.
92 port 1.
95 port@1:
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Dti,j721e-dss.yaml28 - description: common_s1 DSS Shared common 1
30 - description: VIDL1 light video plane 1
32 - description: VID1 video plane 1
38 - description: VP1 video port 1
67 - description: vp1 Video Port 1 pixel clock
81 minItems: 1
85 minItems: 1
92 - description: common_s1 DSS Shared common 1
103 maxItems: 1
116 The output port node form video port 1
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/Documentation/devicetree/bindings/
Ddts-coding-style.rst9 the Devicetree Specification and the dtc compiler (including W=1 and W=2
22 1. Node and property names can use only the following characters:
42 gpi_dma2: dma-controller@a00000 {
50 1. Nodes on any bus, thus using unit addresses for children, shall be
117 1. "compatible"
130 1. Most important properties start the node: compatible then bus addressing to
144 #dma-cells = <1>;
145 clocks = <&clock_controller 0>, <&clock_controller 1>;
147 #address-cells = <1>;
148 #size-cells = <1>;
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/Documentation/devicetree/bindings/dma/
Dti-edma.txt82 1.
120 edma_tptc2: tptc@49a00000 {
196 no-1-8-v;
199 clocks = <&k2g_clks 0xb 1>, <&k2g_clks 0xb 2>;
209 - #dma-cells: Should be set to <1>
213 1. Transfer completion interrupt.
235 #dma-cells = <1>;
236 ti,edma-xbar-event-map = /bits/ 16 <1 12