Searched +full:2 +full:- +full:4 (Results 1 – 25 of 1051) sorted by relevance
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| /Documentation/hwmon/ |
| D | xdpe152c4.rst | 1 .. SPDX-License-Identifier: GPL-2.0
21 -----------
23 This driver implements support for Infineon Digital Multi-phase Controller
27 - Intel VR13, VR13HC and VR14 rev 1.86
29 - Intel SVID rev 1.93. protocol.
30 - PMBus rev 1.3.1 interface.
41 indexes 1, 2 are for "iin" and 3, 4 for "iout":
43 **curr[1-4]_crit**
45 **curr[1-4]_crit_alarm**
47 **curr[1-4]_input**
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| D | lt7182s.rst | 1 .. SPDX-License-Identifier: GPL-2.0
12 Addresses scanned: -
16 Author: Guenter Roeck <linux@roeck-us.net>
20 -----------
22 LT7182S is a Dual Channel 6A, 20V PolyPhase Step-Down Silent Switcher with
27 -----------
33 at address 0x4f on I2C bus #4::
36 # echo lt7182s 0x4f > /sys/bus/i2c/devices/i2c-4/new_device
42 ----------------
45 curr[1-2]_label "iin[12]"
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| D | pxe1610.rst | 10 Addresses scanned: -
18 Addresses scanned: -
26 Addresses scanned: -
34 -----------
36 PXE1610/PXE1110 are Multi-rail/Multiphase Digital Controllers
39 - Intel VR13 DC-DC converter specifications.
40 - Intel SVID protocol.
44 - Servers, Workstations, and High-end desktops
46 PXM1310 is a Multi-rail Controller and it is compliant to
48 - Intel VR13 DC-DC converter specifications.
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| D | xdpe12284.rst | 1 .. SPDX-License-Identifier: GPL-2.0
25 -----------
27 This driver implements support for Infineon Multi-phase XDPE112 and XDPE122
32 - Intel VR13 and VR13HC rev 1.3, IMVP8 rev 1.2 and IMPVP9 rev 1.3 DC-DC
34 - Intel SVID rev 1.9. protocol.
35 - PMBus rev 1.3 interface.
41 - VR12.0 mode, 5-mV DAC - 0x01.
42 - VR12.5 mode, 10-mV DAC - 0x02.
43 - IMVP9 mode, 5-mV DAC - 0x03.
44 - AMD mode 6.25mV - 0x10.
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| /Documentation/input/devices/ |
| D | elantech.rst | 4 Copyright (C) 2007-2008 Arjan Opmeer <arjan@opmeer.net>
9 Version 2 (EeePC) hardware support based on patches
16 2. Extra knobs
18 4. Hardware version 1
20 4.2 Native relative mode 4 byte packet format
21 4.3 Native absolute mode 4 byte packet format
22 5. Hardware version 2
25 5.2.1 Parity checking and packet re-synchronization
26 5.2.2 One/Three finger touch
32 6.2.2 Two finger touch
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| D | sentelic.rst | 8 :Copyright: |copy| 2002-2011 Sentelic Corporation.
10 :Last update: Dec-07-2011
12 Finger Sensing Pad Intellimouse Mode (scrolling wheel, 4th and 5th buttons)
15 A) MSID 4: Scrolling wheel mode plus Forward page(4th button) and Backward
19 2. Set sample rate to 200;
21 4. Issuing the "Get device ID" command (0xF2) and waits for the response;
27 Bit 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
28 BYTE |---------------|BYTE |---------------|BYTE|---------------|BYTE|---------------|
29 1 |Y|X|y|x|1|M|R|L| 2 |X|X|X|X|X|X|X|X| 3 |Y|Y|Y|Y|Y|Y|Y|Y| 4 | | |B|F|W|W|W|W|
30 |---------------| |---------------| |---------------| |---------------|
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| D | alps.rst | 1 ----------------------
3 ----------------------
6 ------------
8 ALPS touchpads, called versions 1, 2, 3, 4, 5, 6, 7 and 8.
10 Since roughly mid-2010 several new ALPS touchpads have been released and
14 adequate. The design choices were to re-define the alps_model_data
29 ---------
32 E8-E6-E6-E6-E9. An ALPS touchpad should respond with either 00-00-0A or
33 00-00-64 if no buttons are pressed. The bits 0-2 of the first byte will be 1s
37 report" sequence: E8-E7-E7-E7-E9. The response is the model signature and is
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| /Documentation/userspace-api/media/v4l/ |
| D | pixfmt-packed-yuv.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _packed-yuv:
15 - In all the tables that follow, bit 7 is the most significant bit in a byte.
16 - 'Y', 'Cb' and 'Cr' denote bits of the luma, blue chroma (also known as
22 4:4:4 Subsampling
28 The next table lists the packed YUV 4:4:4 formats with less than 8 bits per
30 seen in a 16-bit word, which is then stored in memory in little endian byte
32 format stores a pixel in a 16-bit word [15:0] laid out at as [Y'\ :sub:`4-0`
33 Cb\ :sub:`5-0` Cr\ :sub:`4-0`], and stored in memory in two bytes,
34 [Cb\ :sub:`2-0` Cr\ :sub:`4-0`] followed by [Y'\ :sub:`4-0` Cb\ :sub:`5-3`].
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| D | pixfmt-rgb.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _pixfmt-rgb:
22 (including capture queues of mem-to-mem devices) fill the alpha component in
25 but can set the alpha bit to a user-configurable value, the
26 :ref:`V4L2_CID_ALPHA_COMPONENT <v4l2-alpha-component>` control is used to
31 :ref:`Output <output>` devices (including output queues of mem-to-mem devices
44 - In all the tables that follow, bit 7 is the most significant bit in a byte.
45 - 'r', 'g' and 'b' denote bits of the red, green and blue components
54 based on the order of the RGB components as seen in a 8-, 16- or 32-bit word,
56 noted by the presence of bit 31 in the 4CC value), and on the number of bits
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| D | metafmt-vsp1-hgt.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _v4l2-meta-fmt-vsp1-hgt:
9 Renesas R-Car VSP1 2-D Histogram Data
15 This format describes histogram data generated by the Renesas R-Car VSP1
16 2-D Histogram (HGT) engine.
28 The Saturation position **n** (0 - 31) of the bucket in the matrix is
33 The Hue position **m** (0 - 5) of the bucket in the matrix depends on
43 Area 0 Area 1 Area 2 Area 3 Area 4 Area 5
50 5U 0L 0U 1L 1U 2L 2U 3L 3U 4L 4U 5L 5U 0L
72 0L <= 0U <= 1L <= 1U <= 2L <= 2U <= 3L <= 3U <= 4L <= 4U <= 5L <= 5U
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| D | yuv-formats.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _yuv-formats:
29 direction are possible, common factors are 1 (no subsampling), 2 and 4, with
33 - `4:4:4`: No subsampling
34 - `4:2:2`: Horizontal subsampling by 2, no vertical subsampling
35 - `4:2:0`: Horizontal subsampling by 2, vertical subsampling by 2
36 - `4:1:1`: Horizontal subsampling by 4, no vertical subsampling
37 - `4:1:0`: Horizontal subsampling by 4, vertical subsampling by 4
42 - .. _yuv-chroma-centered:
49 - .. _yuv-chroma-cosited:
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| D | subdev-formats.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _v4l2-mbus-format:
14 .. flat-table:: struct v4l2_mbus_framefmt
15 :header-rows: 0
16 :stub-columns: 0
17 :widths: 1 1 2
19 * - __u32
20 - ``width``
21 - Image width in pixels.
22 * - __u32
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| D | pixfmt-yuv-planar.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. planar-yuv:
12 - Semi-planar formats use two planes. The first plane is the luma plane and
16 - Fully planar formats use three planes to store the Y, Cb and Cr components
26 and applications that support the multi-planar API, described in
27 :ref:`planar-apis`. Unless explicitly documented as supporting non-contiguous
31 Semi-Planar YUV Formats
43 line stride. With horizontal subsampling by 2, the chroma line stride is equal
46 For non-contiguous formats, no constraints are enforced by the format on the
57 .. flat-table:: Overview of Semi-Planar YUV Formats
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| /Documentation/translations/zh_CN/core-api/ |
| D | packing.rst | 1 .. SPDX-License-Identifier: GPL-2.0+
3 .. include:: ../disclaimer-zh_CN.rst
5 :Original: Documentation/core-api/packing.rst
22 --------
42 --------
46 - 将一个CPU可使用的数字打包到内存缓冲区中（具有硬件约束/特殊性）。
47 - 将内存缓冲区（具有硬件约束/特殊性）解压缩为一个CPU可使用的数字。
62 7 6 5 4
63 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
64 3 2 1 0
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| /Documentation/devicetree/bindings/sound/ |
| D | qcom,wcd937x-sdw.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/qcom,wcd937x-sdw.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
13 Qualcomm WCD9370/WCD9375 Codec is a standalone Hi-Fi audio codec IC.
24 qcom,tx-port-mapping:
29 Supports maximum 4 tx soundwire ports.
31 WCD9370 TX Port 1 (ADC1) <=> SWR2 Port 2
32 WCD9370 TX Port 2 (ADC2, 3) <=> SWR2 Port 2
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| /Documentation/filesystems/ext4/ |
| D | blocks.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 ------
8 integral power of 2. Blocks are in turn grouped into larger units called
10 4KiB. You may experience mounting problems if block size is greater than
11 page size (i.e. 64KiB blocks on a i386 which only has 4KiB memory
12 pages). By default a filesystem can contain 2^32 blocks; if the '64bit'
13 feature is enabled, then a filesystem can have 2^64 blocks. The location
17 For 32-bit filesystems, limits are as follows:
19 .. list-table::
21 :header-rows: 1
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| /Documentation/driver-api/media/drivers/ |
| D | sh_mobile_ceu_camera.rst | 1 .. SPDX-License-Identifier: GPL-2.0
9 -----------
12 host scales: -"- host driver
17 ---------------------------------
19 .. code-block:: none
21 -1--
23 -2-- -\
24 | --\
25 | --\
26 +-5-- . -- -3-- -\
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| /Documentation/devicetree/bindings/nvmem/ |
| D | socionext,uniphier-efuse.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/nvmem/socionext,uniphier-efuse.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Keiji Hayashibara <hayashibara.keiji@socionext.com>
11 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
14 - $ref: nvmem.yaml#
15 - $ref: nvmem-deprecated-cells.yaml#
19 const: socionext,uniphier-efuse
25 - compatible
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| /Documentation/driver-api/media/drivers/ccs/ |
| D | ccs-regs.asc | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause
2 # Copyright (C) 2019--2020 Intel Corporation
5 # - f field LSB MSB rflags
6 # - e enum value # after a field
7 # - e enum value [LSB MSB]
8 # - b bool bit
9 # - l arg name min max elsize [discontig...]
23 - e GRBG 0
24 - e RGGB 1
25 - e BGGR 2
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| /Documentation/core-api/ |
| D | packing.rst | 6 -----------------
10 One can memory-map a pointer to a carefully crafted struct over the hardware
23 were performed byte-by-byte. Also the code can easily get cluttered, and the
24 high-level idea might get lost among the many bit shifts required.
25 Many drivers take the bit-shifting approach and then attempt to reduce the
30 ------------
32 This API deals with 2 basic operations:
34 - Packing a CPU-usable number into a memory buffer (with hardware
36 - Unpacking a memory buffer (which has hardware constraints/quirks)
37 into a CPU-usable number.
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| /Documentation/devicetree/bindings/regulator/ |
| D | microchip,mcp16502.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MCP16502 - High-Performance PMIC
10 - Andrei Simion <andrei.simion@microchip.com>
16 of High-Performance mode (HPM).
22 lpm-gpios:
26 suspend-to-ram, keeping the PMIC into HIBERNATE mode.
31 lvin-supply:
34 pvin1-supply:
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| /Documentation/devicetree/bindings/crypto/ |
| D | hisilicon,hip07-sec.txt | 4 - compatible: Must contain one of
5 - "hisilicon,hip06-sec"
6 - "hisilicon,hip07-sec"
7 - reg: Memory addresses and lengths of the memory regions through which
11 Regions 2-18 have registers for the 16 individual queues which are isolated
13 - interrupts: Interrupt specifiers.
14 Refer to interrupt-controller/interrupts.txt for generic interrupt client node
17 Interrupt 2N + 1 is the completion interrupt for queue N.
18 Interrupt 2N + 2 is the error interrupt for queue N.
19 - dma-coherent: The driver assumes coherent dma is possible.
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| /Documentation/iio/ |
| D | ad7380.rst | 1 .. SPDX-License-Identifier: GPL-2.0-only
23 * `AD7380-4 <https://www.analog.com/en/products/ad7380-4.html>`_
24 * `AD7381-4 <https://www.analog.com/en/products/ad7381-4.html>`_
25 * `AD7383-4 <https://www.analog.com/en/products/ad7383-4.html>`_
26 * `AD7384-4 <https://www.analog.com/en/products/ad7384-4.html>`_
27 * `AD7386-4 <https://www.analog.com/en/products/ad7386-4.html>`_
28 * `AD7387-4 <https://www.analog.com/en/products/ad7387-4.html>`_
29 * `AD7388-4 <https://www.analog.com/en/products/ad7388-4.html>`_
36 ----------------
38 ad738x ADCs can output data on several SDO lines (1/2/4). The driver currently
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | fsl,intmux.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/fsl,intmux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Guo <shawnguo@kernel.org>
11 - NXP Linux Team <linux-imx@nxp.com>
15 const: fsl,imx-intmux
27 interrupt-controller: true
29 '#interrupt-cells':
30 const: 2
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| /Documentation/devicetree/bindings/dma/ |
| D | milbeaut-m10v-hdmac.txt | 4 - device to memory transfer
5 - memory to device transfer
8 - compatible: Should be "socionext,milbeaut-m10v-hdmac"
9 - reg: Should contain DMA registers location and length.
10 - interrupts: Should contain all of the per-channel DMA interrupts.
11 Number of channels is configurable - 2, 4 or 8, so
12 the number of interrupts specified should be {2,4,8}.
13 - #dma-cells: Should be 1. Specify the ID of the slave.
14 - clocks: Phandle to the clock used by the HDMAC module.
19 hdmac1: dma-controller@1e110000 {
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