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| /Documentation/arch/arm64/ |
| D | asymmetric-32bit.rst | 2 Asymmetric 32-bit SoCs
7 This document describes the impact of asymmetric 32-bit SoCs on the
8 execution of 32-bit (``AArch32``) applications.
10 Date: 2021-05-17
16 of the CPUs are capable of executing 32-bit user applications. On such
19 ``execve(2)`` of 32-bit ELF binaries, with the latter returning
20 ``-ENOEXEC``. If the mismatch is detected during late onlining of a
21 64-bit-only CPU, then the onlining operation fails and the new CPU is
25 running legacy 32-bit binaries. Unsurprisingly, that doesn't work very
28 It seems inevitable that future SoCs will drop 32-bit support
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| D | booting.rst | 13 (EL0 - EL3), with EL0, EL1 and EL2 having a secure and a non-secure
27 2. Setup the device tree
33 ---------------------------
45 2. Setup the device tree
46 -------------------------
50 The device tree blob (dtb) must be placed on an 8-byte boundary and must
51 not exceed 2 megabytes in size. Since the dtb will be mapped cacheable
52 using blocks of up to 2 megabytes in size, it must not be placed within
53 any 2M region which must be mapped with any specific attributes.
55 NOTE: versions prior to v4.2 also require that the DTB be placed within
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| /Documentation/devicetree/bindings/crypto/ |
| D | fsl-sec2.txt | 1 Freescale SoC SEC Security Engines versions 1.x-2.x-3.x
5 - compatible : Should contain entries for this and backward compatible
7 e.g., "fsl,sec1.2", "fsl,sec1.0" (SEC1)
9 - reg : Offset and length of the register set for the device
10 - interrupts : the SEC's interrupt number
11 - fsl,num-channels : An integer representing the number of channels
13 - fsl,channel-fifo-len : An integer representing the number of
15 - fsl,exec-units-mask : The bitmask representing what execution units
16 (EUs) are available. It's a single 32-bit cell. EU information
20 bit 0 = reserved - should be 0
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| /Documentation/devicetree/bindings/mfd/ |
| D | mc13xxx.txt | 4 - compatible : Should be "fsl,mc13783" or "fsl,mc13892"
7 - fsl,mc13xxx-uses-adc : Indicate the ADC is being used
8 - fsl,mc13xxx-uses-codec : Indicate the Audio Codec is being used
9 - fsl,mc13xxx-uses-rtc : Indicate the RTC is being used
10 - fsl,mc13xxx-uses-touch : Indicate the touchscreen controller is being used
12 Sub-nodes:
13 - codec: Contain the Audio Codec node.
14 - adc-port: Contain PMIC SSI port number used for ADC.
15 - dac-port: Contain PMIC SSI port number used for DAC.
16 - leds : Contain the led nodes and initial register values in property
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| /Documentation/devicetree/bindings/gpio/ |
| D | gpio-74xx-mmio.txt | 4 - compatible: Should contain one of the following:
5 "ti,741g125": for 741G125 (1-bit Input),
6 "ti,741g174": for 741G74 (1-bit Output),
7 "ti,742g125": for 742G125 (2-bit Input),
8 "ti,7474" : for 7474 (2-bit Output),
9 "ti,74125" : for 74125 (4-bit Input),
10 "ti,74175" : for 74175 (4-bit Output),
11 "ti,74365" : for 74365 (6-bit Input),
12 "ti,74174" : for 74174 (6-bit Output),
13 "ti,74244" : for 74244 (8-bit Input),
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| D | gpio-mmio.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/gpio-mmio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
11 - Bartosz Golaszewski <brgl@bgdev.pl>
15 of set/clear-bit registers. Such controllers are common for glue logic in
16 FPGAs or ASICs. Commonly, these controllers are accessed over memory-mapped
17 NAND-style parallel busses.
22 - brcm,bcm6345-gpio
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| /Documentation/input/devices/ |
| D | elantech.rst | 4 Copyright (C) 2007-2008 Arjan Opmeer <arjan@opmeer.net>
9 Version 2 (EeePC) hardware support based on patches
16 2. Extra knobs
22 5. Hardware version 2
25 5.2.1 Parity checking and packet re-synchronization
26 5.2.2 One/Three finger touch
32 6.2.2 Two finger touch
37 7.2.2 Head packet
50 hardware versions unimaginatively called version 1,version 2, version 3
52 packet. Version 2 seems to be introduced with the EeePC and uses 6 bytes
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| /Documentation/devicetree/bindings/powerpc/ |
| D | ibm,powerpc-cpu-features.txt | 3 (skiboot/doc/device-tree/ibm,powerpc-cpu-features/binding.txt)
9 ibm,powerpc-cpu-features binding
19 /cpus/ibm,powerpc-cpu-features node binding
20 -------------------------------------------
22 Node: ibm,powerpc-cpu-features
26 The node name must be "ibm,powerpc-cpu-features".
35 - compatible
38 Definition: "ibm,powerpc-cpu-features"
45 - isa
52 implementation that lacks the "transactional-memory" cpufeature node
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| /Documentation/gpu/ |
| D | afbc.rst | 1 .. SPDX-License-Identifier: GPL-2.0+
8 It provides fine-grained random access and minimizes the amount of
21 AFBC streams can contain several components - where a component
33 * Component 2: B
37 reside in the least-significant bits of the corresponding linear
44 * Component 2: B(8)
51 * Component 2: B(8)
56 * Component 1: Cb(8, 2x1 subsampled)
57 * Component 2: Cr(8, 2x1 subsampled)
67 * Component 2: B(8)
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| /Documentation/ABI/testing/ |
| D | sysfs-driver-zynqmp-fpga | 1 What: /sys/bus/platform/drivers/zynqmp_fpga_manager/firmware:zynqmp-firmware:pcap/status
7 of the FPGA device. Each bit position in the status value is
9 https://docs.xilinx.com/v/u/en-US/ug570-ultrascale-configuration
12 BIT(0) 0: No CRC error
15 BIT(1) 0: Decryptor security not set
18 BIT(2) 0: MMCMs/PLLs are not locked
21 BIT(3) 0: DCI not matched
24 BIT(4) 0: Start-up sequence has not finished
25 1: Start-up sequence has finished
27 BIT(5) 0: All I/Os are placed in High-Z state
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| /Documentation/arch/riscv/ |
| D | vector.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 Vector Extension Support for RISC-V Linux
8 order to support the use of the RISC-V Vector Extension.
11 ---------------------
19 are not portable to non-Linux, nor non-RISC-V environments, so it is discourage
21 please read :c:macro:`COMPAT_HWCAP_ISA_V` bit of :c:macro:`ELF_HWCAP` in the
27 argument consists of two 2-bit enablement statuses and a bit for inheritance
30 Enablement status is a tri-state value each occupying 2-bit of space in
33 * :c:macro:`PR_RISCV_V_VSTATE_CTRL_DEFAULT`: Use the system-wide default
34 enablement status on execve(). The system-wide default setting can be
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| /Documentation/userspace-api/media/v4l/ |
| D | pixfmt-sdr-pcu18be.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _V4L2-SDR-FMT-PCU18BE:
9 Planar complex unsigned 18-bit big endian IQ sample
15 number consist of two parts called In-phase and Quadrature (IQ). Both I
16 and Q are represented as a 18 bit unsigned big endian number stored in
17 32 bit space. The remaining unused bits within the 32 bit space will be
19 equalling half of the buffer size (i.e.) offset = buffersize/2. Out of
20 the 18 bits, bit 17:2 (16 bit) is data and bit 1:0 (2 bit) can be any
26 .. flat-table::
27 :header-rows: 1
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| D | pixfmt-sdr-pcu16be.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _V4L2-SDR-FMT-PCU16BE:
9 Planar complex unsigned 16-bit big endian IQ sample
15 number consist of two parts called In-phase and Quadrature (IQ). Both I
16 and Q are represented as a 16 bit unsigned big endian number stored in
17 32 bit space. The remaining unused bits within the 32 bit space will be
19 equalling half of the buffer size (i.e.) offset = buffersize/2. Out of
20 the 16 bits, bit 15:2 (14 bit) is data and bit 1:0 (2 bit) can be any
26 .. flat-table::
27 :header-rows: 1
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| /Documentation/devicetree/bindings/dma/stm32/ |
| D | st,stm32-mdma.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/stm32/st,stm32-mdma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The STM32 MDMA is a general-purpose direct memory access controller capable of
13 described in the dma.txt file, using a five-cell specifier for each channel:
16 2. The priority level
21 3. A 32bit mask specifying the DMA channel configuration
22 -bit 0-1: Source increment mode
26 -bit 2-3: Destination increment mode
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| D | st,stm32-dma.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/stm32/st,stm32-dma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The STM32 DMA is a general-purpose direct memory access controller capable of
13 described in the dma.txt file, using a four-cell specifier for each
16 2. The request line number
17 3. A 32bit mask specifying the DMA channel configuration which are device
19 -bit 9: Peripheral Increment Address
22 -bit 10: Memory Increment Address
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| D | st,stm32-dma3.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/stm32/st,stm32-dma3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
22 described in "#dma-cells" property description below, using a three-cell
26 - Amelie Delaunay <amelie.delaunay@foss.st.com>
29 - $ref: /schemas/dma/dma-controller.yaml#
33 const: st,stm32mp25-dma3
42 Should contain all of the per-channel DMA interrupts in ascending order
51 power-domains:
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| /Documentation/devicetree/bindings/timer/ |
| D | renesas,cmt.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Geert Uytterhoeven <geert+renesas@glider.be>
11 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
14 The CMT is a multi-channel 16/32/48-bit timer/counter with configurable clock
26 - items:
27 - enum:
28 - renesas,r8a7740-cmt0 # 32-bit CMT0 on R-Mobile A1
29 - renesas,r8a7740-cmt1 # 48-bit CMT1 on R-Mobile A1
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| /Documentation/PCI/endpoint/ |
| D | pci-test-function.rst | 1 .. SPDX-License-Identifier: GPL-2.0
11 However with the addition of EP-core in linux kernel, it is possible
22 2) PCI_ENDPOINT_TEST_COMMAND
44 Bit 0 raise legacy IRQ
45 Bit 1 raise MSI IRQ
46 Bit 2 raise MSI-X IRQ
47 Bit 3 read command (read data from RC buffer)
48 Bit 4 write command (write data to RC buffer)
49 Bit 5 copy command (copy data from one RC buffer to another RC buffer)
59 Bit 0 read success
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| /Documentation/devicetree/bindings/leds/ |
| D | register-bit-led.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/leds/register-bit-led.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Register Bit LEDs
10 - Linus Walleij <linus.walleij@linaro.org>
13 Register bit leds are used with syscon multifunctional devices where single
14 bits in a certain register can turn on/off a single LED. The register bit LEDs
20 - $ref: /schemas/leds/common.yaml#
25 The unit-address is in the form of @<reg addr>,<bit offset>
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| /Documentation/devicetree/bindings/sound/ |
| D | everest,es8326.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - David Yang <yangxiaohua@everest-semi.com>
21 - description: clock for master clock (MCLK)
23 clock-names:
25 - const: mclk
27 "#sound-dai-cells":
30 everest,jack-pol:
33 just the value of reg 57. Bit(3) decides whether the jack polarity is inverted.
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| /Documentation/networking/device_drivers/cellular/qualcomm/ |
| D | rmnet.rst | 1 .. SPDX-License-Identifier: GPL-2.0
24 sending aggregated bunch of MAP frames. rmnet driver will de-aggregate
27 2. Packet format
36 Bit 0 1 2-7 8-15 16-31
39 Bit 32-x
42 Command (1)/ Data (0) bit value is to indicate if the packet is a MAP command
62 Bit 0 1 2-7 8-15 16-31
65 Bit 32-(x-33) (x-32)-x
68 Command (1)/ Data (0) bit value is to indicate if the packet is a MAP command
87 Bit 0-14 15 16-31
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| /Documentation/devicetree/bindings/soc/imx/ |
| D | fsl,imx-anatop.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/imx/fsl,imx-anatop.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Guo <shawnguo@kernel.org>
11 - Sascha Hauer <s.hauer@pengutronix.de>
16 - items:
17 - enum:
18 - fsl,imx6sl-anatop
19 - fsl,imx6sll-anatop
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| /Documentation/devicetree/bindings/reset/ |
| D | intel,rcu-gw.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/reset/intel,rcu-gw.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dilip Kota <eswara.kota@linux.intel.com>
15 - intel,rcu-lgm
16 - intel,rcu-xrx200
22 intel,global-reset:
23 description: Global reset register offset and bit offset.
24 $ref: /schemas/types.yaml#/definitions/uint32-array
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| /Documentation/devicetree/bindings/ |
| D | trivial-devices.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/trivial-devices.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
27 spi-max-frequency: true
32 - enum:
34 - acbel,fsg032
35 … # SMBus/I2C Digital Temperature Sensor in 6-Pin SOT with SMBus Alert and Over Temperature Pin
36 - ad,ad7414 # Deprecated, use adi,ad7414
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| /Documentation/devicetree/bindings/regulator/ |
| D | anatop-regulator.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/regulator/anatop-regulator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
13 - $ref: regulator.yaml#
17 const: fsl,anatop-regulator
19 regulator-name: true
21 anatop-reg-offset:
25 anatop-vol-bit-shift:
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